Sunit Tyagi

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,888,710
- Issue date Feb 15, 2011
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Active region spacer for semiconductor devices and method to form t...
- Patent number 7,560,780
- Issue date Jul 14, 2009
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with strain-inducing structure in channel
- Patent number 7,473,591
- Issue date Jan 6, 2009
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained silicon MOS device with box layer between the source and d...
- Patent number 7,422,950
- Issue date Sep 9, 2008
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device with stepped source/drain region profile
- Patent number 7,335,959
- Issue date Feb 26, 2008
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,312,485
- Issue date Dec 25, 2007
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with strain-inducing structure in channel
- Patent number 7,019,326
- Issue date Mar 28, 2006
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor device having an ultra-thin high-...
- Patent number 6,787,440
- Issue date Sep 7, 2004
- Intel Corporation
- Christopher G. Parker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High power PMOS device
- Patent number 6,458,667
- Issue date Oct 1, 2002
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric MOSFET devices
- Patent number 6,384,457
- Issue date May 7, 2002
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for making semiconductor device with epitaxially grown sour...
- Patent number 6,372,583
- Issue date Apr 16, 2002
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to produce asymmetric MOSFET devices
- Patent number 6,297,104
- Issue date Oct 2, 2001
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using epitaxially grown wells for reducing junction capacitances
- Patent number 6,249,025
- Issue date Jun 19, 2001
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using epitaxially grown wells for reducing junction capacitances
- Patent number 6,200,879
- Issue date Mar 13, 2001
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High power PMOS device
- Patent number 6,177,705
- Issue date Jan 23, 2001
- Intel Corporation
- Sunit Tyagi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single poly devices for monitoring the level and polarity of proces...
- Patent number 5,844,300
- Issue date Dec 1, 1998
- Intel Corporation
- Mohsen Alavi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Short channel effect of MOS devices by retrograde well engineering...
- Publication number 20080311720
- Publication date Dec 18, 2008
- Thomas Hoffman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION
- Publication number 20080036005
- Publication date Feb 14, 2008
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a MOSFET transistor having an anti-halo for m...
- Publication number 20070145495
- Publication date Jun 28, 2007
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Isolation body for semiconductor devices and method to form the same
- Publication number 20070132034
- Publication date Jun 14, 2007
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Active region spacer for semiconductor devices and method to form t...
- Publication number 20070132057
- Publication date Jun 14, 2007
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained silicon MOS device with box layer between the source and d...
- Publication number 20070134859
- Publication date Jun 14, 2007
- Intel Corporation
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sacrificial capping layer for transistor performance enhancement
- Publication number 20070004114
- Publication date Jan 4, 2007
- Seok-Hee Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device with stepped source/drain region profile
- Publication number 20060145273
- Publication date Jul 6, 2006
- Giuseppe Curello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor with strain-inducing structure in channel
- Publication number 20060084216
- Publication date Apr 20, 2006
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Short channel effect of MOS devices by retrograde well engineering...
- Publication number 20060065937
- Publication date Mar 30, 2006
- Thomas Hoffmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistor with strain-inducing structure in channel
- Publication number 20050106792
- Publication date May 19, 2005
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for making a semiconductor device having an ultra-thin high-...
- Publication number 20040110361
- Publication date Jun 10, 2004
- Christopher G. Parker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact input/output signal driver for electrostatic discharge prot...
- Publication number 20040080356
- Publication date Apr 29, 2004
- Scott A. Hareland
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS fabrication process utilizing special transistor orientation
- Publication number 20020063292
- Publication date May 30, 2002
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC MOSFET DEVICES
- Publication number 20010013628
- Publication date Aug 16, 2001
- SUNIT TYAGI
- H01 - BASIC ELECTRIC ELEMENTS

Sunit Tyagi

Person

Patents Grantslast 30 patents

CMOS fabrication process utilizing special transistor orientation

Active region spacer for semiconductor devices and method to form t...

Transistor with strain-inducing structure in channel

Strained silicon MOS device with box layer between the source and d...

Device with stepped source/drain region profile

CMOS fabrication process utilizing special transistor orientation

Transistor with strain-inducing structure in channel

Method for making a semiconductor device having an ultra-thin high-...

High power PMOS device

Asymmetric MOSFET devices

Process for making semiconductor device with epitaxially grown sour...

Methods to produce asymmetric MOSFET devices

Using epitaxially grown wells for reducing junction capacitances

Using epitaxially grown wells for reducing junction capacitances

High power PMOS device

Single poly devices for monitoring the level and polarity of proces...

Patents Applicationslast 30 patents

Short channel effect of MOS devices by retrograde well engineering...

CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION

Method of fabricating a MOSFET transistor having an anti-halo for m...

Isolation body for semiconductor devices and method to form the same

Active region spacer for semiconductor devices and method to form t...

Strained silicon MOS device with box layer between the source and d...

Sacrificial capping layer for transistor performance enhancement

Device with stepped source/drain region profile

Transistor with strain-inducing structure in channel

Short channel effect of MOS devices by retrograde well engineering...

Transistor with strain-inducing structure in channel

Method for making a semiconductor device having an ultra-thin high-...

Compact input/output signal driver for electrostatic discharge prot...

CMOS fabrication process utilizing special transistor orientation

ASYMMETRIC MOSFET DEVICES