Supratim Pal

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 12,039,001
- Issue date Jul 16, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing structured sparsity in systolic arrays
- Patent number 11,977,885
- Issue date May 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 11,669,490
- Issue date Jun 6, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,669,329
- Issue date Jun 6, 2023
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for systolic dot product with accumulate
- Patent number 11,640,297
- Issue date May 2, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 11,636,174
- Issue date Apr 25, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a single instruction set architecture (ISA) instruction for...
- Patent number 11,593,069
- Issue date Feb 28, 2023
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register sharing mechanism to equally allocate disabled thread regi...
- Patent number 11,579,878
- Issue date Feb 14, 2023
- Intel Corporation
- Pratik J. Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control flow mechanism for execution of graphics processor instruct...
- Patent number 11,537,403
- Issue date Dec 27, 2022
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical general register file (GRF) for execution block
- Patent number 11,507,375
- Issue date Nov 22, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix optimization mechanism
- Patent number 11,443,407
- Issue date Sep 13, 2022
- Intel Corporation
- Namita Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,361,496
- Issue date Jun 14, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,321,799
- Issue date May 3, 2022
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,314,515
- Issue date Apr 26, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 11,204,977
- Issue date Dec 21, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 11,182,337
- Issue date Nov 23, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a single instruction set architecture (ISA) instruction for...
- Patent number 11,157,238
- Issue date Oct 26, 2021
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix optimization mechanism
- Patent number 11,127,108
- Issue date Sep 21, 2021
- Intel Corporation
- Namita Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for systolic dot product with accumulate
- Patent number 11,042,370
- Issue date Jun 22, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical general register file (GRF) for execution block
- Patent number 11,010,163
- Issue date May 18, 2021
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control flow mechanism for execution of graphics processor instruct...
- Patent number 10,990,409
- Issue date Apr 27, 2021
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register sharing mechanism
- Patent number 10,983,794
- Issue date Apr 20, 2021
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accumulator pooling mechanism
- Patent number 10,839,478
- Issue date Nov 17, 2020
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic thread splitting having multiple instruction pointers for t...
- Patent number 10,789,071
- Issue date Sep 29, 2020
- Intel Corporation
- Hema C. Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recompiling GPU code based on spill/fill instructions and number of...
- Patent number 10,698,689
- Issue date Jun 30, 2020
- Intel Corporation
- Pratik J. Ashar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,692,170
- Issue date Jun 23, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical general register file (GRF) for execution block
- Patent number 10,423,415
- Issue date Sep 24, 2019
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,360,654
- Issue date Jul 23, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Source operand read suppression for graphics processors
- Patent number 10,152,452
- Issue date Dec 11, 2018
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction that performs a scatter write
- Patent number 9,880,839
- Issue date Jan 30, 2018
- Intel Corporation
- Wei-Yu Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20240427847
- Publication date Dec 26, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
- Publication number 20230297373
- Publication date Sep 21, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20230281272
- Publication date Sep 7, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING
- Publication number 20220326953
- Publication date Oct 13, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20220156343
- Publication date May 19, 2022
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A SINGLE INSTRUCTION SET ARCHITECTURE (ISA) INSTRUCTION FOR...
- Publication number 20220147316
- Publication date May 12, 2022
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20220129266
- Publication date Apr 28, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE MATRIX OPTIMIZATION MECHANISM
- Publication number 20220092723
- Publication date Mar 24, 2022
- Intel Corporation
- Namita Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20220058158
- Publication date Feb 24, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20210365402
- Publication date Nov 25, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK
- Publication number 20210349715
- Publication date Nov 11, 2021
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20210349966
- Publication date Nov 11, 2021
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS
- Publication number 20210349717
- Publication date Nov 11, 2021
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20210312697
- Publication date Oct 7, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
- Publication number 20210303299
- Publication date Sep 30, 2021
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCT...
- Publication number 20210286626
- Publication date Sep 16, 2021
- Intel Corporation
- Subramaniam M. Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING
- Publication number 20210191724
- Publication date Jun 24, 2021
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER ASSISTED REGISTER FILE WRITE REDUCTION
- Publication number 20210192673
- Publication date Jun 24, 2021
- Intel Corporation
- Chandra S. GURRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE MATRIX OPTIMIZATION MECHANISM
- Publication number 20210183002
- Publication date Jun 17, 2021
- Intel Corporation
- Namita Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A SINGLE INSTRUCTION SET ARCHITECTURE (ISA) INSTRUCTION FOR...
- Publication number 20210149635
- Publication date May 20, 2021
- Intel Corporation
- Abhishek Rhisheekesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERA...
- Publication number 20210089316
- Publication date Mar 25, 2021
- Intel Corporation
- William RASH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20210081201
- Publication date Mar 18, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SHARING MECHANISM
- Publication number 20200394041
- Publication date Dec 17, 2020
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCUMULATOR POOLING MECHANISM
- Publication number 20200320662
- Publication date Oct 8, 2020
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SHARING MECHANISM
- Publication number 20200285471
- Publication date Sep 10, 2020
- Intel Corporation
- PRATIK J. ASHAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER SHARING MECHANISM
- Publication number 20200073664
- Publication date Mar 5, 2020
- Intel Corporation
- PRATIK J. ASHAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK
- Publication number 20200026514
- Publication date Jan 23, 2020
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION
- Publication number 20190362460
- Publication date Nov 28, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
- Publication number 20190324746
- Publication date Oct 24, 2019
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fusion of SIMD Processing Units
- Publication number 20190265973
- Publication date Aug 29, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING

Supratim Pal

Person

Patents Grantslast 30 patents

Scalable sparse matrix multiply acceleration using systolic arrays...

Utilizing structured sparsity in systolic arrays

Computing efficient cross channel operations in parallel computing...

Instructions and logic for vector multiply add with zero skipping

Instruction and logic for systolic dot product with accumulate

Scalable sparse matrix multiply acceleration using systolic arrays...

Use of a single instruction set architecture (ISA) instruction for...

Register sharing mechanism to equally allocate disabled thread regi...

Control flow mechanism for execution of graphics processor instruct...

Hierarchical general register file (GRF) for execution block

Sparse matrix optimization mechanism

Graphics processors and graphics processing units having dot produc...

Compiler assisted register file write reduction

Instructions and logic for vector multiply add with zero skipping

Scalable sparse matrix multiply acceleration using systolic arrays...

Computing efficient cross channel operations in parallel computing...

Use of a single instruction set architecture (ISA) instruction for...

Sparse matrix optimization mechanism

Instruction and logic for systolic dot product with accumulate

Hierarchical general register file (GRF) for execution block

Control flow mechanism for execution of graphics processor instruct...

Register sharing mechanism

Accumulator pooling mechanism

Dynamic thread splitting having multiple instruction pointers for t...

Recompiling GPU code based on spill/fill instructions and number of...

Software scoreboard information and synchronization

Hierarchical general register file (GRF) for execution block

Software scoreboard information and synchronization

Source operand read suppression for graphics processors

Instruction that performs a scatter write

Patents Applicationslast 30 patents

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

USE OF A SINGLE INSTRUCTION SET ARCHITECTURE (ISA) INSTRUCTION FOR...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

SPARSE MATRIX OPTIMIZATION MECHANISM

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE

CONTROL FLOW MECHANISM FOR EXECUTION OF GRAPHICS PROCESSOR INSTRUCT...

INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING

COMPILER ASSISTED REGISTER FILE WRITE REDUCTION

SPARSE MATRIX OPTIMIZATION MECHANISM

USE OF A SINGLE INSTRUCTION SET ARCHITECTURE (ISA) INSTRUCTION FOR...

DEEP LEARNING IMPLEMENTATIONS USING SYSTOLIC ARRAYS AND FUSED OPERA...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

REGISTER SHARING MECHANISM

ACCUMULATOR POOLING MECHANISM

REGISTER SHARING MECHANISM

REGISTER SHARING MECHANISM

HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK

SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE

Fusion of SIMD Processing Units