Supratim PAL

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Supporting 8-bit floating point format operands in a computing arch...
- Patent number 12,242,846
- Issue date Mar 4, 2025
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large integer multiplication enhancements for graphics environment
- Patent number 12,236,238
- Issue date Feb 25, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register allocation sizes for threads
- Patent number 12,210,905
- Issue date Jan 28, 2025
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual pipeline parallel systolic array
- Patent number 12,189,571
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using sparsity metadata to reduce systolic array power consumption
- Patent number 12,190,158
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic array of arbitrary physical and logical depth
- Patent number 12,174,783
- Issue date Dec 24, 2024
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 12,093,213
- Issue date Sep 17, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,900,502
- Issue date Feb 13, 2024
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...
- Publication number 20250037347
- Publication date Jan 30, 2025
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
- Publication number 20250036361
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20240256274
- Publication date Aug 1, 2024
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE
- Publication number 20240168807
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX TRANSPOSITION IN MATRIX MULTIPLICATION ARRAY CIRCUITRY
- Publication number 20240168723
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...
- Publication number 20240169021
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...
- Publication number 20240168764
- Publication date May 23, 2024
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...
- Publication number 20240111609
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING
- Publication number 20240112295
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC BROADCASTING FROM SHARED MEMORY
- Publication number 20240111534
- Publication date Apr 4, 2024
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...
- Publication number 20240103810
- Publication date Mar 28, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20230367740
- Publication date Nov 16, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORWARD PROGRESS GUARANTEE USING SINGLE-LEVEL SYNCHRONIZATION AT IN...
- Publication number 20230153176
- Publication date May 18, 2023
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A G...
- Publication number 20230088743
- Publication date Mar 23, 2023
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED INSTRUCTION TO ACCELERATE PERFORMANCE OF SECURE HASH ALGORITH...
- Publication number 20220416999
- Publication date Dec 29, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20220414054
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER FILE FOR SYSTOLIC ARRAY
- Publication number 20220413851
- Publication date Dec 29, 2022
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
- Publication number 20220413924
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE
- Publication number 20220413854
- Publication date Dec 29, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS
- Publication number 20220413916
- Publication date Dec 29, 2022
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY
- Publication number 20220413803
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT
- Publication number 20220413848
- Publication date Dec 29, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20220414053
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20220318013
- Publication date Oct 6, 2022
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER ASSISTED REGISTER FILE WRITE REDUCTION
- Publication number 20220261949
- Publication date Aug 18, 2022
- Intel Corporation
- Chandra S. GURRAM
- G06 - COMPUTING CALCULATING COUNTING

Supratim PAL

Person

Patents Grantslast 30 patents

Supporting 8-bit floating point format operands in a computing arch...

Large integer multiplication enhancements for graphics environment

Multiple register allocation sizes for threads

Dual pipeline parallel systolic array

Using sparsity metadata to reduce systolic array power consumption

Systolic array of arbitrary physical and logical depth

Computing efficient cross channel operations in parallel computing...

Compiler assisted register file write reduction

Patents Applicationslast 30 patents

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

FLOATING-POINT CONVERSION VIA AN INTEGER UNIT

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

CROSS-THREAD REGISTER SHARING FOR MATRIX MULTIPLICATION COMPUTE

MATRIX TRANSPOSITION IN MATRIX MULTIPLICATION ARRAY CIRCUITRY

ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...

SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...

SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...

SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING

DETERMINISTIC BROADCASTING FROM SHARED MEMORY

SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

FORWARD PROGRESS GUARANTEE USING SINGLE-LEVEL SYNCHRONIZATION AT IN...

GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A G...

FUSED INSTRUCTION TO ACCELERATE PERFORMANCE OF SECURE HASH ALGORITH...

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

REGISTER FILE FOR SYSTOLIC ARRAY

USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION

64-BIT TWO-DIMENSIONAL BLOCK LOAD WITH TRANSPOSE

MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS

SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY

LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

COMPILER ASSISTED REGISTER FILE WRITE REDUCTION