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Suresh Balasubramanian

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  • Cupertino, CA, US
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Patents Grantslast 30 patents

  • Information Patent Grant

    Hybrid pulse/two-stage data latch
    • Patent number 11,870,442
    • Issue date Jan 9, 2024
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Grant

    Clock duty cycle correction
    • Patent number 11,762,413
    • Issue date Sep 19, 2023
    • Apple Inc.
    • Suresh Balasubramanian
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Grant

    Hybrid pulse/two-stage data latch
    • Patent number 11,418,173
    • Issue date Aug 16, 2022
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Grant

    Hybrid pulse/master-slave data latch
    • Patent number 10,742,201
    • Issue date Aug 11, 2020
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

  • Information Patent Application

    Hybrid Pulse/Two-Stage Data Latch
    • Publication number 20220345117
    • Publication date Oct 27, 2022
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    CLOCK DUTY CYCLE CORRECTION
    • Publication number 20220103166
    • Publication date Mar 31, 2022
    • Apple Inc.
    • Suresh Balasubramanian
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    Hybrid Pulse/Two-Stage Data Latch
    • Publication number 20200373915
    • Publication date Nov 26, 2020
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    HYBRID PULSE/MASTER-SLAVE DATA LATCH
    • Publication number 20200106425
    • Publication date Apr 2, 2020
    • Apple Inc.
    • Vivekanandan Venugopal
    • G06 - COMPUTING CALCULATING COUNTING