Suresh K. Marisetty

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System abstraction layer, processor abstraction layer, and operatin...
- Patent number 7,904,751
- Issue date Mar 8, 2011
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for redirection of machine check interrupts in...
- Patent number 7,721,148
- Issue date May 18, 2010
- Intel Corporation
- Scott Brenden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for error injection using a flexible program inte...
- Patent number 7,587,639
- Issue date Sep 8, 2009
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
OS and firmware coordinated error handling using transparent firmwa...
- Patent number 7,546,487
- Issue date Jun 9, 2009
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable error handling apparatus and methods to operate the same
- Patent number 7,533,300
- Issue date May 12, 2009
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction apparatus, systems, and methods
- Patent number 7,502,959
- Issue date Mar 10, 2009
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Poisoned error signaling for proactive OS recovery
- Patent number 7,353,433
- Issue date Apr 1, 2008
- Intel Corporation
- Kushagra Vaid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling errors in a processing system
- Patent number 7,308,610
- Issue date Dec 11, 2007
- Intel Corporation
- Rajendra Kuramkote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable CPU error recorder
- Patent number 7,117,396
- Issue date Oct 3, 2006
- Intel Corporation
- Eshwari P. Komarla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Algorithm for non-volatile memory updates
- Patent number 6,754,828
- Issue date Jun 22, 2004
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rendezvous of processors with OS coordination
- Patent number 6,675,324
- Issue date Jan 6, 2004
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System abstraction layer, processor abstraction layer, and operatin...
- Patent number 6,622,260
- Issue date Sep 16, 2003
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 6,047,355
- Issue date Apr 4, 2000
- Intel Corporation
- William S. Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enabling application programs to continue...
- Patent number 5,925,117
- Issue date Jul 20, 1999
- Intel Corporation
- Graham D. Kirby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptively generating timing signals for access to various memory d...
- Patent number 5,809,340
- Issue date Sep 15, 1998
- Packard Bell NEC
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system with data conference capability
- Patent number 5,793,961
- Issue date Aug 11, 1998
- Intel Corporation
- Suresh K. Marisetty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for sharing hardward resources in a computer s...
- Patent number 5,768,598
- Issue date Jun 16, 1998
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing bit block transfers in a comput...
- Patent number 5,666,521
- Issue date Sep 9, 1997
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for emulating circuitry in a computer system u...
- Patent number 5,590,312
- Issue date Dec 31, 1996
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing power consumption in a computer s...
- Patent number 5,590,342
- Issue date Dec 31, 1996
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus grant prediction technique for a split transaction bus in a mul...
- Patent number 5,574,868
- Issue date Nov 12, 1996
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric multiprocessing system with unified environment and distr...
- Patent number 5,522,069
- Issue date May 28, 1996
- Zenith Data Systems Corporation
- James F. Bertone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexed byte enable bus for partial word writes to ECC protecte...
- Patent number 5,369,651
- Issue date Nov 29, 1994
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus stretching protocol for handling invalid data
- Patent number 5,271,020
- Issue date Dec 14, 1993
- Intel Corporation
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for redirection of machine check interrupts in...
- Publication number 20080005615
- Publication date Jan 3, 2008
- Scott Brenden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable error handling apparatus and methods to operate the same
- Publication number 20070220332
- Publication date Sep 20, 2007
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OS and firmware coordinated error handling using transparent firmwa...
- Publication number 20070061634
- Publication date Mar 15, 2007
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for handling errors in a processing system
- Publication number 20060143515
- Publication date Jun 29, 2006
- Rajendra Kuramkote
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for error injection using a flexible program inte...
- Publication number 20060112307
- Publication date May 25, 2006
- Suresh K. Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Poisoned error signaling for proactive OS recovery
- Publication number 20050138487
- Publication date Jun 23, 2005
- Intel Corporation (a Delaware corporation)
- Kushagra Vaid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error correction apparatus, systems, and methods
- Publication number 20040095833
- Publication date May 20, 2004
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System abstraction layer, processor abstraction layer, and operatin...
- Publication number 20040019835
- Publication date Jan 29, 2004
- Intel Corporation
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable CPU error recorder
- Publication number 20030126516
- Publication date Jul 3, 2003
- Eshwari P. Komarla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RENDEZVOUS OF PROCESSORS WITH OS COORDINATION
- Publication number 20030051190
- Publication date Mar 13, 2003
- SURESH MARISETTY
- G06 - COMPUTING CALCULATING COUNTING

Suresh K. Marisetty

Person

Patents Grantslast 30 patents

System abstraction layer, processor abstraction layer, and operatin...

Method and apparatus for redirection of machine check interrupts in...

System and method for error injection using a flexible program inte...

OS and firmware coordinated error handling using transparent firmwa...

Configurable error handling apparatus and methods to operate the same

Error correction apparatus, systems, and methods

Poisoned error signaling for proactive OS recovery

Method and apparatus for handling errors in a processing system

Scalable CPU error recorder

Algorithm for non-volatile memory updates

Rendezvous of processors with OS coordination

System abstraction layer, processor abstraction layer, and operatin...

Symmetric multiprocessing system with unified environment and distr...

Method and apparatus for enabling application programs to continue...

Adaptively generating timing signals for access to various memory d...

Computer system with data conference capability

Method and apparatus for sharing hardward resources in a computer s...

Method and apparatus for performing bit block transfers in a comput...

Method and apparatus for emulating circuitry in a computer system u...

Method and apparatus for reducing power consumption in a computer s...

Bus grant prediction technique for a split transaction bus in a mul...

Symmetric multiprocessing system with unified environment and distr...

Multiplexed byte enable bus for partial word writes to ECC protecte...

Bus stretching protocol for handling invalid data

Patents Applicationslast 30 patents

Method and apparatus for redirection of machine check interrupts in...

Configurable error handling apparatus and methods to operate the same

OS and firmware coordinated error handling using transparent firmwa...

Method and apparatus for handling errors in a processing system

System and method for error injection using a flexible program inte...

Poisoned error signaling for proactive OS recovery

Error correction apparatus, systems, and methods

System abstraction layer, processor abstraction layer, and operatin...

Scalable CPU error recorder

RENDEZVOUS OF PROCESSORS WITH OS COORDINATION