Suresh M. Menon

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit having embedded differential clock tree
- Patent number 7,759,973
- Issue date Jul 20, 2010
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,617,472
- Issue date Nov 10, 2009
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data alignment and deskewing module
- Patent number 7,551,646
- Issue date Jun 23, 2009
- Xilinx, Inc.
- Qi Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,518,401
- Issue date Apr 14, 2009
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having an embedded differential clock tree
- Patent number 7,414,430
- Issue date Aug 19, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,372,299
- Issue date May 13, 2008
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Regional signal-distribution network for an integrated circuit
- Patent number 7,353,487
- Issue date Apr 1, 2008
- Xilinx, Inc.
- Jason R. Bergendahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate flip-flop
- Patent number 7,317,773
- Issue date Jan 8, 2008
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High speed configurable transceiver architecture
- Patent number 7,187,709
- Issue date Mar 6, 2007
- Xilinx, Inc.
- Suresh M. Menon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential clock tree in an integrated circuit
- Patent number 7,129,765
- Issue date Oct 31, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having an embedded differential clock tree
- Patent number 7,126,406
- Issue date Oct 24, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network physical layer with embedded multi-standard CRC generator
- Patent number 7,111,220
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Paul T. Sasaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-purpose source synchronous interface circuitry
- Patent number 7,091,890
- Issue date Aug 15, 2006
- Xilinx, Inc.
- Paul T. Sasaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Variable data width operation in multi-gigabit transceivers on a pr...
- Patent number 6,960,933
- Issue date Nov 1, 2005
- Xilinx, Inc.
- Warren E. Cory
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and circuit for hot swap protection
- Patent number 6,810,458
- Issue date Oct 26, 2004
- Xilinx, Inc.
- Hassan K. Bazargan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate flip-flop
- Patent number 6,777,980
- Issue date Aug 17, 2004
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Variable data width operation in multi-gigabit transceivers on a pr...
- Patent number 6,617,877
- Issue date Sep 9, 2003
- Xilinx, Inc.
- Warren E. Cory
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Double data rate flip-flop
- Patent number 6,525,565
- Issue date Feb 25, 2003
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration memory architecture for FPGA
- Patent number 6,501,677
- Issue date Dec 31, 2002
- Xilinx, Inc.
- Prasad Rau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally controlled impedance for I/O of an integrated circuit device
- Patent number 6,489,837
- Issue date Dec 3, 2002
- Xilinx, Inc.
- David P. Schultz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digitally controlled impedance for I/O of an integrated circuit device
- Patent number 6,445,245
- Issue date Sep 3, 2002
- Xilinx, Inc.
- David P. Schultz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit for producing low-voltage differential signals
- Patent number 6,366,128
- Issue date Apr 2, 2002
- Xilinx, Inc.
- Atul V. Ghia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration memory architecture for FPGA
- Patent number 6,222,757
- Issue date Apr 24, 2001
- Xilinx, Inc.
- Prasad Rau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable input/output circuit for FPGA for use in TTL, GTL, GTL...
- Patent number 6,218,858
- Issue date Apr 17, 2001
- Xilinx, Inc.
- Suresh Manohar Menon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scaleable padframe interface circuit for FPGA yielding improved rou...
- Patent number 6,130,550
- Issue date Oct 10, 2000
- Dynalogic
- Arch Zaliznyak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Duty cycle controller for clock signal to synchronous SRAM on FPGA
- Patent number 5,940,606
- Issue date Aug 17, 1999
- Dynachip Corporation
- Atul V. Ghia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed programmable logic architecture
- Patent number 5,808,479
- Issue date Sep 15, 1998
- Dyna Logic Corporation
- Paul T. Sasaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic cell with input polarity control
- Patent number 5,744,981
- Issue date Apr 28, 1998
- Dyna Logic Corporation
- Paul T. Sasaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic bias driver
- Patent number 5,654,665
- Issue date Aug 5, 1997
- Dynachip Corporation
- Suresh M. Menon
- G05 - CONTROLLING REGULATING
Information Patent Grant
High speed programmable logic architecture
- Patent number 5,614,844
- Issue date Mar 25, 1997
- Dyna Logic Corporation
- Paul T. Sasaki
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20070013428
- Publication date Jan 18, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20060290403
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20060290402
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20050242865
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20050242866
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Double data rate flip-flop
- Publication number 20040239365
- Publication date Dec 2, 2004
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Double data rate flip-flop
- Publication number 20030112032
- Publication date Jun 19, 2003
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Double data rate flip-flop
- Publication number 20020175704
- Publication date Nov 28, 2002
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digitally controlled impedance for I/O of an integrated circuit device
- Publication number 20020101278
- Publication date Aug 1, 2002
- Xilinx, Inc.
- David P. Schultz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Suresh M. Menon

Person

Patents Grantslast 30 patents

Integrated circuit having embedded differential clock tree

Regional signal-distribution network for an integrated circuit

Data alignment and deskewing module

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Differential clock tree in an integrated circuit

Regional signal-distribution network for an integrated circuit

Double data rate flip-flop

High speed configurable transceiver architecture

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Network physical layer with embedded multi-standard CRC generator

Multi-purpose source synchronous interface circuitry

Variable data width operation in multi-gigabit transceivers on a pr...

Method and circuit for hot swap protection

Double data rate flip-flop

Variable data width operation in multi-gigabit transceivers on a pr...

Double data rate flip-flop

Configuration memory architecture for FPGA

Digitally controlled impedance for I/O of an integrated circuit device

Digitally controlled impedance for I/O of an integrated circuit device

Circuit for producing low-voltage differential signals

Configuration memory architecture for FPGA

Programmable input/output circuit for FPGA for use in TTL, GTL, GTL...

Scaleable padframe interface circuit for FPGA yielding improved rou...

Duty cycle controller for clock signal to synchronous SRAM on FPGA

High speed programmable logic architecture

Programmable logic cell with input polarity control

Programmable logic bias driver

High speed programmable logic architecture

Patents Applicationslast 30 patents

Differential clock tree in an integrated circuit

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Double data rate flip-flop

Double data rate flip-flop

Double data rate flip-flop

Digitally controlled impedance for I/O of an integrated circuit device