Suresh Pothukuchi

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optical multichip package with multiple system-on-chip dies
- Patent number 12,148,744
- Issue date Nov 19, 2024
- Intel Corporation
- Zhichao Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided co-packaged optics for high bandwidth networking applica...
- Patent number 11,830,863
- Issue date Nov 28, 2023
- Intel Corporation
- Suresh V. Pothukuchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided co-packaged optics for high bandwidth networking applica...
- Patent number 11,217,573
- Issue date Jan 4, 2022
- Intel Corporation
- Suresh V. Pothukuchi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Die-stacking using through-silicon vias on bumpless build-up layer...
- Patent number 9,406,618
- Issue date Aug 2, 2016
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die-stacking using through-silicon vias on bumpless build-up layer...
- Patent number 8,786,066
- Issue date Jul 22, 2014
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES
- Publication number 20250038163
- Publication date Jan 30, 2025
- Intel Corporation
- Zhichao ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SLIT FIDUCIALS FOR INTEGRATED CIRCUIT DEVICE ALIGNMENT
- Publication number 20250006651
- Publication date Jan 2, 2025
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS
- Publication number 20230401130
- Publication date Dec 14, 2023
- Intel Corporation
- Rakesh Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES
- Publication number 20220199600
- Publication date Jun 23, 2022
- Intel Corporation
- Zhichao ZHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES
- Publication number 20220155539
- Publication date May 19, 2022
- Intel Corporation
- Srinivas V. PIETAMBARAM
- G02 - OPTICS
Information Patent Application
DUAL-SIDED CO-PACKAGED OPTICS FOR HIGH BANDWIDTH NETWORKING APPLICA...
- Publication number 20220085001
- Publication date Mar 17, 2022
- Intel Corporation
- Suresh V. POTHUKUCHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-SIDED CO-PACKAGED OPTICS FOR HIGH BANDWIDTH NETWORKING APPLICA...
- Publication number 20210280566
- Publication date Sep 9, 2021
- Intel Corporation
- Suresh V. POTHUKUCHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGING SOLUTIONS FOR HIGH BANDWIDTH NETWORKING APPLICATIONS
- Publication number 20210210478
- Publication date Jul 8, 2021
- Intel Corporation
- Susheel JADHAV
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...
- Publication number 20140327149
- Publication date Nov 6, 2014
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...
- Publication number 20140295621
- Publication date Oct 2, 2014
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...
- Publication number 20120074581
- Publication date Mar 29, 2012
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS

Suresh Pothukuchi

Person

Patents Grantslast 30 patents

Optical multichip package with multiple system-on-chip dies

Dual-sided co-packaged optics for high bandwidth networking applica...

Dual-sided co-packaged optics for high bandwidth networking applica...

Die-stacking using through-silicon vias on bumpless build-up layer...

Die-stacking using through-silicon vias on bumpless build-up layer...

Patents Applicationslast 30 patents

OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES

SLIT FIDUCIALS FOR INTEGRATED CIRCUIT DEVICE ALIGNMENT

FPGA BASED PLATFORM FOR POST-SILICON VALIDATION OF CHIPLETS

OPTICAL MULTICHIP PACKAGE WITH MULTIPLE SYSTEM-ON-CHIP DIES

HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES

DUAL-SIDED CO-PACKAGED OPTICS FOR HIGH BANDWIDTH NETWORKING APPLICA...

DUAL-SIDED CO-PACKAGED OPTICS FOR HIGH BANDWIDTH NETWORKING APPLICA...

PACKAGING SOLUTIONS FOR HIGH BANDWIDTH NETWORKING APPLICATIONS

DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...

DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...

DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER...