Suresh Rajgopal

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Serial interface for an active input/output expander of a memory su...
- Patent number 12,130,755
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ball grid array storage for a memory sub-system
- Patent number 11,886,358
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management of erase suspend and resume operations in memory devices
- Patent number 11,861,207
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Chandra M. Guda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active input/output expander of a memory sub-system
- Patent number 11,675,696
- Issue date Jun 13, 2023
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of host-initiated requests in memory sub-systems
- Patent number 11,614,890
- Issue date Mar 28, 2023
- Micron Technology, Inc.
- Marc S. Hamilton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing sequential write performance consistency for memory devices
- Patent number 11,455,107
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus having a multiplexer for passive input/output expansion
- Patent number 11,385,949
- Issue date Jul 12, 2022
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection component that is configured based on an architecture ass...
- Patent number 11,347,415
- Issue date May 31, 2022
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ball grid array storage for a memory sub-system
- Patent number 11,301,401
- Issue date Apr 12, 2022
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management of erase suspend and resume operations in memory devices
- Patent number 11,237,754
- Issue date Feb 1, 2022
- Micron Technology, Inc.
- Chandra M. Guda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying write performance to prolong life of a physical memory de...
- Patent number 11,182,087
- Issue date Nov 23, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active input/output expander of a memory sub-system
- Patent number 11,132,292
- Issue date Sep 28, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection component that is configured based on an architecture ass...
- Patent number 10,877,678
- Issue date Dec 29, 2020
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus having multiplexers for passive input/output expansion an...
- Patent number 10,846,158
- Issue date Nov 24, 2020
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low density parity check circuit
- Patent number 9,411,684
- Issue date Aug 9, 2016
- Micron Technology, Inc.
- Joe F. Holt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method using hashing for efficiently implementing an...
- Patent number 8,295,286
- Issue date Oct 23, 2012
- STMicroelectronics, Inc.
- Suresh Rajgopal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism to reduce lookup latency in a pipelined hardware implemen...
- Patent number 7,924,839
- Issue date Apr 12, 2011
- STMicroelectronics, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method of using fully configurable memory, multi-stag...
- Patent number 7,782,853
- Issue date Aug 24, 2010
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for path compression optimization in a pipelined...
- Patent number 7,715,392
- Issue date May 11, 2010
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for increasing storage capacity in a multi-bit trie-based ha...
- Patent number 7,162,481
- Issue date Jan 9, 2007
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for increasing average storage capacity in a bit-mapped tree...
- Patent number 7,099,881
- Issue date Aug 29, 2006
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS
- Publication number 20230359390
- Publication date Nov 9, 2023
- Micron Technology, Inc.
- Jose Rey C. De Luna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PEAK POWER MANAGEMENT PRIORITY OVERRIDE
- Publication number 20230350587
- Publication date Nov 2, 2023
- Micron Technology, Inc.
- Jeremy Binfet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SU...
- Publication number 20230075279
- Publication date Mar 9, 2023
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALL GRID ARRAY STORAGE FOR A MEMORY SUB-SYSTEM
- Publication number 20220237131
- Publication date Jul 28, 2022
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES
- Publication number 20220121385
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chandra M. Guda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM
- Publication number 20210406172
- Publication date Dec 30, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM
- Publication number 20210173771
- Publication date Jun 10, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES
- Publication number 20210173580
- Publication date Jun 10, 2021
- Micron Technology, Inc.
- Chandra M. Guda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASS...
- Publication number 20210117115
- Publication date Apr 22, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING SEQUENTIAL WRITE PERFORMANCE CONSISTENCY FOR MEMORY DEVICES
- Publication number 20210096755
- Publication date Apr 1, 2021
- Micron Technology, Inc.
- Suresh RAJGOPAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFYING WRITE PERFORMANCE TO PROLONG LIFE OF A PHYSICAL MEMORY DE...
- Publication number 20210096756
- Publication date Apr 1, 2021
- Micron Technology, Inc.
- Suresh RAJGOPAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING ATTRIBUTES OF MEMORY COMPONENTS
- Publication number 20210064278
- Publication date Mar 4, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS HAVING A MULTIPLEXER FOR PASSIVE INPUT/OUTPUT EXPANSION
- Publication number 20210055979
- Publication date Feb 25, 2021
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING OF HOST-INITIATED REQUESTS IN MEMORY SUB-SYSTEMS
- Publication number 20210034290
- Publication date Feb 4, 2021
- Micron Technology, Inc.
- Marc S. Hamilton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PASSIVE INPUT/OUTPUT EXPANSION
- Publication number 20200110645
- Publication date Apr 9, 2020
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASS...
- Publication number 20190354301
- Publication date Nov 21, 2019
- Micron Technology, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW DENSITY PARITY CHECK CIRCUIT
- Publication number 20150270851
- Publication date Sep 24, 2015
- Micron Technology, Inc.
- Joe F. Holt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method using hashing for efficiently implementing an...
- Publication number 20050141519
- Publication date Jun 30, 2005
- STMicroelectronics, Inc.
- Suresh Rajgopal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for path compression optimization in a pipelined...
- Publication number 20040114587
- Publication date Jun 17, 2004
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Mechanism to reduce lookup latency in a pipelined hardware implemen...
- Publication number 20040111395
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method of using fully configurable memory, multi-stag...
- Publication number 20040109451
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for increasing storage capacity in a multi-bit trie-based ha...
- Publication number 20040111440
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for increasing average storage capacity in a bit-mapped tree...
- Publication number 20040111439
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING

Suresh Rajgopal

Person

Patents Grantslast 30 patents

Serial interface for an active input/output expander of a memory su...

Ball grid array storage for a memory sub-system

Management of erase suspend and resume operations in memory devices

Active input/output expander of a memory sub-system

Handling of host-initiated requests in memory sub-systems

Managing sequential write performance consistency for memory devices

Apparatus having a multiplexer for passive input/output expansion

Selection component that is configured based on an architecture ass...

Ball grid array storage for a memory sub-system

Management of erase suspend and resume operations in memory devices

Modifying write performance to prolong life of a physical memory de...

Active input/output expander of a memory sub-system

Selection component that is configured based on an architecture ass...

Apparatus having multiplexers for passive input/output expansion an...

Low density parity check circuit

Apparatus and method using hashing for efficiently implementing an...

Mechanism to reduce lookup latency in a pipelined hardware implemen...

Apparatus and method of using fully configurable memory, multi-stag...

System and method for path compression optimization in a pipelined...

Method for increasing storage capacity in a multi-bit trie-based ha...

Method for increasing average storage capacity in a bit-mapped tree...

Patents Applicationslast 30 patents

CONFIGURABLE BUFFERED I/O FOR MEMORY SYSTEMS

PEAK POWER MANAGEMENT PRIORITY OVERRIDE

SERIAL INTERFACE FOR AN ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SU...

BALL GRID ARRAY STORAGE FOR A MEMORY SUB-SYSTEM

MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES

ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM

ACTIVE INPUT/OUTPUT EXPANDER OF A MEMORY SUB-SYSTEM

MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES

SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASS...

MANAGING SEQUENTIAL WRITE PERFORMANCE CONSISTENCY FOR MEMORY DEVICES

MODIFYING WRITE PERFORMANCE TO PROLONG LIFE OF A PHYSICAL MEMORY DE...

MANAGING ATTRIBUTES OF MEMORY COMPONENTS

APPARATUS HAVING A MULTIPLEXER FOR PASSIVE INPUT/OUTPUT EXPANSION

HANDLING OF HOST-INITIATED REQUESTS IN MEMORY SUB-SYSTEMS

PASSIVE INPUT/OUTPUT EXPANSION

SELECTION COMPONENT THAT IS CONFIGURED BASED ON AN ARCHITECTURE ASS...

LOW DENSITY PARITY CHECK CIRCUIT

Apparatus and method using hashing for efficiently implementing an...

System and method for path compression optimization in a pipelined...

Mechanism to reduce lookup latency in a pipelined hardware implemen...

Apparatus and method of using fully configurable memory, multi-stag...

Method for increasing storage capacity in a multi-bit trie-based ha...

Method for increasing average storage capacity in a bit-mapped tree...