Suresh S. Chittor

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory utilized as both system memory and near memory
- Patent number 11,567,877
- Issue date Jan 31, 2023
- Intel Corporation
- Suresh S. Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to reduce power consumption for refresh of mem...
- Patent number 11,250,902
- Issue date Feb 15, 2022
- Intel Corporation
- Douglas Heymann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for setting a 2-level auto-close timer to access a memor...
- Patent number 11,216,386
- Issue date Jan 4, 2022
- Intel Corporation
- Vivek Kozhikkottu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for application specific address mapping
- Patent number 10,936,507
- Issue date Mar 2, 2021
- Intel Corporation
- Vivek Kozhikkottu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing memory and I/O services between nodes
- Patent number 10,915,468
- Issue date Feb 9, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link level retry scheme
- Patent number 7,991,875
- Issue date Aug 2, 2011
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mitigating silent data corruption in a buffered memory module archi...
- Patent number 7,734,980
- Issue date Jun 8, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silent data corruption mitigation using error correction code with...
- Patent number 7,644,347
- Issue date Jan 5, 2010
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for sharing channels by interleaving flits
- Patent number 7,486,685
- Issue date Feb 3, 2009
- Linda J. Rankin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link level retry scheme
- Patent number 7,016,304
- Issue date Mar 21, 2006
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Coherent variable length reads from system memory
- Patent number 6,298,420
- Issue date Oct 2, 2001
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for deferring transactions on a host bus havin...
- Patent number 6,195,722
- Issue date Feb 27, 2001
- Intel Corporation
- Rajee Ram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective conflict write flush
- Patent number 6,145,062
- Issue date Nov 7, 2000
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherent variable length reads which implicates multiple cache line...
- Patent number 6,061,764
- Issue date May 9, 2000
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and an apparatus for minimizing perturbation while monitorin...
- Patent number 6,021,457
- Issue date Feb 1, 2000
- Intel Corporation
- David W. Archer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus protocol for atomic transactions
- Patent number 5,987,552
- Issue date Nov 16, 1999
- Intel Corporation
- Suresh Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing the fault-tolerance of a network
- Patent number 5,592,610
- Issue date Jan 7, 1997
- Intel Corporation
- Suresh S. Chittor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20240160585
- Publication date May 16, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20220012189
- Publication date Jan 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20210303482
- Publication date Sep 30, 2021
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, Apparatus And Method For Application Specific Address Mapping
- Publication number 20200310979
- Publication date Oct 1, 2020
- Intel Corporation
- Vivek Kozhikkottu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION FOR REFRESH OF MEM...
- Publication number 20200027500
- Publication date Jan 23, 2020
- Intel Corporation
- Douglas HEYMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMOR...
- Publication number 20200019513
- Publication date Jan 16, 2020
- Intel Corporation
- Vivek KOZHIKKOTTU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY UTILIZED AS BOTH SYSTEM MEMORY AND NEAR MEMORY
- Publication number 20190258583
- Publication date Aug 22, 2019
- Intel Corporation
- Suresh S. Chittor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR LOCAL DISAGGREGATION OF MEMORY
- Publication number 20190065415
- Publication date Feb 28, 2019
- Intel Corporation
- Murugasamy K. Nachimuthu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING MEMORY AND I/O SERVICES BETWEEN NODES
- Publication number 20170004098
- Publication date Jan 5, 2017
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Firm partitioning in a system with a point-to-point interconnect
- Publication number 20070150699
- Publication date Jun 28, 2007
- Ioannis T. Schoinas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Link level retry scheme
- Publication number 20070130353
- Publication date Jun 7, 2007
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Silent data corruption mitigation using error correction code with...
- Publication number 20070089035
- Publication date Apr 19, 2007
- Intel Corporation
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mitigating silent data corruption in a buffered memory module archi...
- Publication number 20070011562
- Publication date Jan 11, 2007
- James W. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for sharing channels by interleaving flits
- Publication number 20030002493
- Publication date Jan 2, 2003
- Linda J. Rankin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Link level retry scheme
- Publication number 20020172164
- Publication date Nov 21, 2002
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Suresh S. Chittor

Person

Patents Grantslast 30 patents

Memory utilized as both system memory and near memory

Method and apparatus to reduce power consumption for refresh of mem...

Techniques for setting a 2-level auto-close timer to access a memor...

System, apparatus and method for application specific address mapping

Sharing memory and I/O services between nodes

Link level retry scheme

Mitigating silent data corruption in a buffered memory module archi...

Silent data corruption mitigation using error correction code with...

System for sharing channels by interleaving flits

Link level retry scheme

Coherent variable length reads from system memory

Method and apparatus for deferring transactions on a host bus havin...

Selective conflict write flush

Coherent variable length reads which implicates multiple cache line...

Method and an apparatus for minimizing perturbation while monitorin...

Bus protocol for atomic transactions

Method and apparatus for enhancing the fault-tolerance of a network

Patents Applicationslast 30 patents

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

System, Apparatus And Method For Application Specific Address Mapping

METHOD AND APPARATUS TO REDUCE POWER CONSUMPTION FOR REFRESH OF MEM...

TECHNIQUES FOR SETTING A 2-LEVEL AUTO-CLOSE TIMER TO ACCESS A MEMOR...

MEMORY UTILIZED AS BOTH SYSTEM MEMORY AND NEAR MEMORY

TECHNOLOGIES FOR LOCAL DISAGGREGATION OF MEMORY

SHARING MEMORY AND I/O SERVICES BETWEEN NODES

Firm partitioning in a system with a point-to-point interconnect

Link level retry scheme

Silent data corruption mitigation using error correction code with...

Mitigating silent data corruption in a buffered memory module archi...

System for sharing channels by interleaving flits

Link level retry scheme