Suryanarayan G. Hegde

Person

New York, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned planar double-gate transistor structure
- Patent number 7,453,123
- Issue date Nov 18, 2008
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned planar double-gate process by self-aligned oxidation
- Patent number 7,205,185
- Issue date Apr 17, 2007
- International Busniess Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS performance enhancement using localized voids and extended def...
- Patent number 6,878,978
- Issue date Apr 12, 2005
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS performance enhancement using localized voids and extended def...
- Patent number 6,858,488
- Issue date Feb 22, 2005
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned planar double-gate process by amorphization
- Patent number 6,833,569
- Issue date Dec 21, 2004
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS performance enhancement using localized voids and extended def...
- Patent number 6,803,270
- Issue date Oct 12, 2004
- International Business Machines Corporation
- Omer H. Dokumachi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Orientation independent oxidation of nitrided silicon
- Patent number 6,727,142
- Issue date Apr 27, 2004
- International Business Machines Corporation
- Oleg Gluschenkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an ultra-thin oxide layer on a silicon substrate...
- Patent number 6,569,781
- Issue date May 27, 2003
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of enhanced oxidation of MOS transistor gate corners
- Patent number 6,514,843
- Issue date Feb 4, 2003
- International Business Machines Corporation
- Omer Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process of forming an ultra-shallow junction dopant layer having a...
- Patent number 6,387,782
- Issue date May 14, 2002
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a uniform gate oxide of a vertical transistor
- Patent number 6,348,388
- Issue date Feb 19, 2002
- International Business Machines Corporation
- Johnathan E. Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-shallow junction dopant layer having a peak concentration wit...
- Patent number 6,329,704
- Issue date Dec 11, 2001
- International Business Machines Corporation
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Application of excimer laser anneal to DRAM processing
- Patent number 6,297,086
- Issue date Oct 2, 2001
- International Business Machines Corporation
- Suryanarayan G. Hegde
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabricating a uniform gate oxide of a vertical transistor
- Patent number 6,150,670
- Issue date Nov 21, 2000
- International Business Machines Corporation
- Johnathan E. Faltermeier
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE
- Publication number 20080246090
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION
- Publication number 20070138556
- Publication date Jun 21, 2007
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS performance enhancement using localized voids and extended def...
- Publication number 20050148134
- Publication date Jul 7, 2005
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned planar double-gate process by self-aligned oxidation
- Publication number 20050059252
- Publication date Mar 17, 2005
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS performance enhancement using localized voids and extended def...
- Publication number 20050003604
- Publication date Jan 6, 2005
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEF...
- Publication number 20050003605
- Publication date Jan 6, 2005
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEF...
- Publication number 20040166624
- Publication date Aug 26, 2004
- International Business Machines Corporation
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned planar double-gate process by amorphization
- Publication number 20040121549
- Publication date Jun 24, 2004
- Omer H. Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORIENTATION INDEPENDENT OXIDATION OF NITRIDED SILICON
- Publication number 20040082197
- Publication date Apr 29, 2004
- International Business Machines Corporation
- Oleg Gluschenkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method of providing reduced programming voltage antifuse
- Publication number 20040051162
- Publication date Mar 18, 2004
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming variable oxide thicknesses across semiconductor c...
- Publication number 20020197836
- Publication date Dec 26, 2002
- International Business Machines Corporation
- S. Sundar Kumar Iyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of enhanced oxidation of MOS transistor gate corners
- Publication number 20020160593
- Publication date Oct 31, 2002
- International Business Machines Corporation
- Omer Dokumaci
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of forming an ultra-shallow junction dopant layer having a...
- Publication number 20010030333
- Publication date Oct 18, 2001
- Hiroyuki Akatsu
- H01 - BASIC ELECTRIC ELEMENTS

Suryanarayan G. Hegde

Person

Patents Grantslast 30 patents

Self-aligned planar double-gate transistor structure

Self-aligned planar double-gate process by self-aligned oxidation

CMOS performance enhancement using localized voids and extended def...

CMOS performance enhancement using localized voids and extended def...

Self-aligned planar double-gate process by amorphization

CMOS performance enhancement using localized voids and extended def...

Orientation independent oxidation of nitrided silicon

Method of forming an ultra-thin oxide layer on a silicon substrate...

Method of enhanced oxidation of MOS transistor gate corners

Process of forming an ultra-shallow junction dopant layer having a...

Process for fabricating a uniform gate oxide of a vertical transistor

Ultra-shallow junction dopant layer having a peak concentration wit...

Application of excimer laser anneal to DRAM processing

Process for fabricating a uniform gate oxide of a vertical transistor

Patents Applicationslast 30 patents

SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE

SELF-ALIGNED PLANAR DOUBLE-GATE PROCESS BY SELF-ALIGNED OXIDATION

CMOS performance enhancement using localized voids and extended def...

Self-aligned planar double-gate process by self-aligned oxidation

CMOS performance enhancement using localized voids and extended def...

CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEF...

CMOS PERFORMANCE ENHANCEMENT USING LOCALIZED VOIDS AND EXTENDED DEF...

Self-aligned planar double-gate process by amorphization

ORIENTATION INDEPENDENT OXIDATION OF NITRIDED SILICON

Structure and method of providing reduced programming voltage antifuse

Method of forming variable oxide thicknesses across semiconductor c...

Method of enhanced oxidation of MOS transistor gate corners

Process of forming an ultra-shallow junction dopant layer having a...