Swadesh Choudhary

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Encoder and decoder of forward error correction (FEC) codec
- Patent number 12,244,326
- Issue date Mar 4, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical physical layer interface specification support for PCie 6.0...
- Patent number 12,222,881
- Issue date Feb 11, 2025
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forward error correction and cyclic redundancy check mechanisms for...
- Patent number 12,189,470
- Issue date Jan 7, 2025
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible on-die fabric interface
- Patent number 12,111,783
- Issue date Oct 8, 2024
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for controlling traffic in a fabric
- Patent number 12,032,500
- Issue date Jul 9, 2024
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer-PHY interface adapter
- Patent number 11,971,841
- Issue date Apr 30, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared resources for multiple communication traffics
- Patent number 11,818,058
- Issue date Nov 14, 2023
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Encoder and decoder of forward error correction (FEC) codec
- Patent number 11,770,138
- Issue date Sep 26, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming fabric interface
- Patent number 11,762,802
- Issue date Sep 19, 2023
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible on-die fabric interface
- Patent number 11,698,879
- Issue date Jul 11, 2023
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for increasing bandwidth of edge-locat...
- Patent number 11,294,850
- Issue date Apr 5, 2022
- Intel Corporation
- Brinda Ganesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache agent trace and capture
- Patent number 11,281,562
- Issue date Mar 22, 2022
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared resources for multiple communication traffics
- Patent number 11,088,967
- Issue date Aug 10, 2021
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated input/output management
- Patent number 10,860,515
- Issue date Dec 8, 2020
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache agent trace and capture
- Patent number 10,534,687
- Issue date Jan 14, 2020
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mission-critical computing architecture
- Patent number 10,514,990
- Issue date Dec 24, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LINK LAYER-PHY INTERFACE ADAPTER
- Publication number 20250013600
- Publication date Jan 9, 2025
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...
- Publication number 20240345983
- Publication date Oct 17, 2024
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE
- Publication number 20240329129
- Publication date Oct 3, 2024
- Intel Corporation
- Sridhar Muthrasanallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC
- Publication number 20230370095
- Publication date Nov 16, 2023
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE ON-DIE FABRIC INTERFACE
- Publication number 20230350829
- Publication date Nov 2, 2023
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING FABRIC INTERFACE
- Publication number 20230342323
- Publication date Oct 26, 2023
- Mohannad Fahim Ali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
CXL-CACHE/MEM PROTOCOL INTERFACE (CPI) LATENCY REDUCTION MECHANISM
- Publication number 20230237168
- Publication date Jul 27, 2023
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE LEVEL CONTROL IN A DATA PROCESSING APPARATUS
- Publication number 20230236651
- Publication date Jul 27, 2023
- Intel Corporation
- UJJWAL GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
- Publication number 20220334995
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
- Publication number 20220318111
- Publication date Oct 6, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTION OF PROCESSING MODE FOR RECEIVER CIRCUIT
- Publication number 20220308954
- Publication date Sep 29, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
- Publication number 20220271912
- Publication date Aug 25, 2022
- Gerald Pasdast
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220262756
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220261308
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
- Publication number 20220237138
- Publication date Jul 28, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS
- Publication number 20220222198
- Publication date Jul 14, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE LOGGING FOR LANE MARGINING AND CHARACTERIZATION
- Publication number 20220012140
- Publication date Jan 13, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED RESOURCES FOR MULTIPLE COMMUNICATION TRAFFICS
- Publication number 20210409351
- Publication date Dec 30, 2021
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0...
- Publication number 20210232520
- Publication date Jul 29, 2021
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR...
- Publication number 20210119730
- Publication date Apr 22, 2021
- Intel Corporation
- Debendra Das Sharma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM, APPARATUS AND METHOD FOR HANDLING MULTI-PROTOCOL TRAFFIC IN...
- Publication number 20210112132
- Publication date Apr 15, 2021
- NITISH PALIWAL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Swadesh Choudhary

Person

Patents Grantslast 30 patents

Encoder and decoder of forward error correction (FEC) codec

Logical physical layer interface specification support for PCie 6.0...

Forward error correction and cyclic redundancy check mechanisms for...

Flexible on-die fabric interface

System, apparatus and method for controlling traffic in a fabric

Link layer-PHY interface adapter

Shared resources for multiple communication traffics

Encoder and decoder of forward error correction (FEC) codec

Streaming fabric interface

Flexible on-die fabric interface

System, apparatus and method for increasing bandwidth of edge-locat...

Method and system for cache agent trace and capture

Shared resources for multiple communication traffics

Integrated input/output management

Method and system for cache agent trace and capture

Mission-critical computing architecture

Patents Applicationslast 30 patents

LINK LAYER-PHY INTERFACE ADAPTER

APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING MANAGEMENT TRANSPORT...

TECHNOLOGIES FOR A UNIFIED TEST AND DEBUG ARCHITECTURE

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

ENCODER AND DECODER OF FORWARD ERROR CORRECTION (FEC) CODEC

FLEXIBLE ON-DIE FABRIC INTERFACE

STREAMING FABRIC INTERFACE

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

CXL-CACHE/MEM PROTOCOL INTERFACE (CPI) LATENCY REDUCTION MECHANISM

PERFORMANCE LEVEL CONTROL IN A DATA PROCESSING APPARATUS

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS

COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT

SELECTION OF PROCESSING MODE FOR RECEIVER CIRCUIT

CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT

CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS

VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS

LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT

SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS

HARDWARE LOGGING FOR LANE MARGINING AND CHARACTERIZATION

SHARED RESOURCES FOR MULTIPLE COMMUNICATION TRAFFICS

LOGICAL PHYSICAL LAYER INTERFACE SPECIFICATION SUPPORT FOR PCIE 6.0...

FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR...

SYSTEM, APPARATUS AND METHOD FOR HANDLING MULTI-PROTOCOL TRAFFIC IN...