Swapnil Bahl

Person

New Delhi, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scan compression architecture for highly compressed designs and ass...
- Patent number 10,354,742
- Issue date Jul 16, 2019
- STMicroelectronics International N.V.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan compression architecture for highly compressed designs and ass...
- Patent number 9,606,180
- Issue date Mar 28, 2017
- STMicroelectronics International N.V.
- Swapnil Bahl
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous on-chip clock controllers
- Patent number 9,264,049
- Issue date Feb 16, 2016
- STMicroelectronics International N.V.
- Swapnil Bahl
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Monitoring on-chip clock control during integrated circuit testing
- Patent number 9,234,938
- Issue date Jan 12, 2016
- STMicroelectronics International N.V.
- Shray Khullar
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with reduced power consumption in a test mode, a...
- Patent number 8,917,123
- Issue date Dec 23, 2014
- STMicroelectronics International N.V.
- Swapnil Bahl
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential on-chip clock controller with dynamic bypass for multi-c...
- Patent number 8,775,857
- Issue date Jul 8, 2014
- STMicroelectronics International N.V.
- Shray Khullar
- G01 - MEASURING TESTING
Information Patent Grant
Testing of multi-clock domains
- Patent number 8,527,824
- Issue date Sep 3, 2013
- STMicroelectronics International N.V.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing of a memory with redundancy elements
- Patent number 8,458,545
- Issue date Jun 4, 2013
- STMicroelectronics International N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of multi-clock domains
- Patent number 8,381,051
- Issue date Feb 19, 2013
- STMicroelectronics International N.V.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Grant
Self programmable shared bist for testing multiple memories
- Patent number 7,814,385
- Issue date Oct 12, 2010
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip storage memory for storing variable data bits
- Patent number 7,372,755
- Issue date May 13, 2008
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip and at-speed tester for testing and characterization of dif...
- Patent number 7,353,442
- Issue date Apr 1, 2008
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable length first-in first-out memory
- Patent number 7,321,520
- Issue date Jan 22, 2008
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...
- Publication number 20170140838
- Publication date May 18, 2017
- STMicroelectronics International N.V
- Swapnil BAHL
- G01 - MEASURING TESTING
Information Patent Application
SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...
- Publication number 20150323593
- Publication date Nov 12, 2015
- STMicroelectronics International N.V
- Swapnil BAHL
- G01 - MEASURING TESTING
Information Patent Application
MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING
- Publication number 20150323594
- Publication date Nov 12, 2015
- STMicroelectronics International N.V
- Shray Khullar
- G01 - MEASURING TESTING
Information Patent Application
SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS
- Publication number 20150137862
- Publication date May 21, 2015
- STMicroelectronics International N.V
- Swapnil Bahl
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, A...
- Publication number 20140292385
- Publication date Oct 2, 2014
- STMicroelectronics International N.V
- SWAPNIL BAHL
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF MULTI-CLOCK DOMAINS
- Publication number 20130159802
- Publication date Jun 20, 2013
- STMicroelectronics International N.V
- Swapnil BAHL
- G01 - MEASURING TESTING
Information Patent Application
SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-C...
- Publication number 20120166860
- Publication date Jun 28, 2012
- STMICROELECTRONICS PVT. LTD.
- Shray Khullar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS
- Publication number 20120137188
- Publication date May 31, 2012
- STMICROELECTRONICS PVT. LTD.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF MULTI-CLOCK DOMAINS
- Publication number 20110264971
- Publication date Oct 27, 2011
- STMICROELECTRONICS PVT. LTD.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Application
SELF PROGRAMMABLE SHARED BIST FOR TESTING MULTIPLE MEMORIES
- Publication number 20080059850
- Publication date Mar 6, 2008
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable length first-in first-out memory
- Publication number 20060256636
- Publication date Nov 16, 2006
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip and at-speed tester for testing and characterization of dif...
- Publication number 20050246602
- Publication date Nov 3, 2005
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G01 - MEASURING TESTING
Information Patent Application
On-chip storage memory for storing variable data bits
- Publication number 20050232028
- Publication date Oct 20, 2005
- STMicroelectronics Pvt. Ltd.
- Swapnil Bahl
- G06 - COMPUTING CALCULATING COUNTING

Swapnil Bahl

Person

Patents Grantslast 30 patents

Scan compression architecture for highly compressed designs and ass...

Scan compression architecture for highly compressed designs and ass...

Synchronous on-chip clock controllers

Monitoring on-chip clock control during integrated circuit testing

Integrated circuit with reduced power consumption in a test mode, a...

Sequential on-chip clock controller with dynamic bypass for multi-c...

Testing of multi-clock domains

Method and apparatus for testing of a memory with redundancy elements

Testing of multi-clock domains

Self programmable shared bist for testing multiple memories

On-chip storage memory for storing variable data bits

On-chip and at-speed tester for testing and characterization of dif...

Configurable length first-in first-out memory

Patents Applicationslast 30 patents

SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...

SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASS...

MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING

SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS

INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, A...

TESTING OF MULTI-CLOCK DOMAINS

SEQUENTIAL ON-CHIP CLOCK CONTROLLER WITH DYNAMIC BYPASS FOR MULTI-C...

METHOD AND APPARATUS FOR TESTING OF A MEMORY WITH REDUNDANCY ELEMENTS

TESTING OF MULTI-CLOCK DOMAINS

SELF PROGRAMMABLE SHARED BIST FOR TESTING MULTIPLE MEMORIES

Configurable length first-in first-out memory

On-chip and at-speed tester for testing and characterization of dif...

On-chip storage memory for storing variable data bits