Swaroop Adusumilli

Person

Tempe, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method to facilitate flexible control of bus drivers dur...
- Patent number 6,543,018
- Issue date Apr 1, 2003
- Koninklijke Philips Electronics N.V.
- Swaroop Adusumilli
- G01 - MEASURING TESTING
Information Patent Grant
System and method to reduce power consumption in advanced RISC mach...
- Patent number 6,438,700
- Issue date Aug 20, 2002
- Koninklijke Philips Electronics N.V.
- Swaroop Adusumilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to reduce scan test pins on an integrated circuit
- Patent number 6,418,545
- Issue date Jul 9, 2002
- Koninklijke Philips Electronics N.V.
- Swaroop Adusumilli
- G01 - MEASURING TESTING
Information Patent Grant
System and method to optimize read performance while accepting writ...
- Patent number 6,412,030
- Issue date Jun 25, 2002
- Koninklijke Philips Electronics N.V.
- Swaroop Adusumilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and arrangement for controlling multiple test access port co...
- Patent number 6,385,749
- Issue date May 7, 2002
- KoninKlijke Philips Electronics N.V. (KPENV)
- Swaroop Adusumilli
- G01 - MEASURING TESTING
Information Patent Grant
Method and arrangement for controlling multiply-activated test acce...
- Patent number 6,334,198
- Issue date Dec 25, 2001
- KoninKlijke Philips Electronics N.V. (KPENV)
- Swaroop Adusumilli
- G01 - MEASURING TESTING
Information Patent Grant
Method and arrangement for hierarchical control of multiple test ac...
- Patent number 6,311,302
- Issue date Oct 30, 2001
- Philips Semiconductor, Inc.
- David Cassetti
- G01 - MEASURING TESTING
Information Patent Grant
Memory mapping method for eliminating dual address cycles in a peri...
- Patent number 6,301,631
- Issue date Oct 9, 2001
- VLSI Technology, Inc.
- Peter Chambers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing the performance of asynchronous bus bridges with dynamic...
- Patent number 6,289,406
- Issue date Sep 11, 2001
- VLSI Technology, Inc.
- Peter Chambers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for eliminating dual address cycles in a peripheral componen...
- Patent number 6,230,216
- Issue date May 8, 2001
- VLSI Technology, Inc.
- Peter Chambers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to predict configuration of a bus target
- Patent number 6,223,232
- Issue date Apr 24, 2001
- VLSI Technology, Inc.
- Swaroop Adusumilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Smart target mechanism for eliminating dual address cycles in a per...
- Patent number 6,178,478
- Issue date Jan 23, 2001
- VLSI Technology, Inc.
- Peter Chambers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for direct access to main memory by an I/O bus
- Patent number 5,815,675
- Issue date Sep 29, 1998
- VLSI Technology, Inc.
- James C. Steele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for arbitrating access to main memory of a com...
- Patent number 5,793,992
- Issue date Aug 11, 1998
- VLSI Technology, Inc.
- James C. Steele
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deadlock resolution methods and apparatus for interfacing concurren...
- Patent number 5,761,454
- Issue date Jun 2, 1998
- VLSI Technology, Inc.
- Swaroop Adusumilli
- G06 - COMPUTING CALCULATING COUNTING

Swaroop Adusumilli

Person

Patents Grantslast 30 patents

System and method to facilitate flexible control of bus drivers dur...

System and method to reduce power consumption in advanced RISC mach...

System and method to reduce scan test pins on an integrated circuit

System and method to optimize read performance while accepting writ...

Method and arrangement for controlling multiple test access port co...

Method and arrangement for controlling multiply-activated test acce...

Method and arrangement for hierarchical control of multiple test ac...

Memory mapping method for eliminating dual address cycles in a peri...

Optimizing the performance of asynchronous bus bridges with dynamic...

Method for eliminating dual address cycles in a peripheral componen...

System and method to predict configuration of a bus target

Smart target mechanism for eliminating dual address cycles in a per...

Method and apparatus for direct access to main memory by an I/O bus

Method and apparatus for arbitrating access to main memory of a com...

Deadlock resolution methods and apparatus for interfacing concurren...