Sylvain Garnier

Person

Nantes, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for integrity checking of code or data in a mix...
- Patent number 10,872,043
- Issue date Dec 22, 2020
- Microchip Technology Incorporated
- Laurent Le Goffic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory emulation mechanism
- Patent number 10,204,057
- Issue date Feb 12, 2019
- Atmel Corporation
- Frode Milch Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor maintaining reset-state after reset signal is suspended
- Patent number 9,423,843
- Issue date Aug 23, 2016
- Atmel Corporation
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automating digital display
- Patent number 9,146,887
- Issue date Sep 29, 2015
- Atmel Corporation
- Sebastien Jouin
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Hot-plugging debugger architectures
- Patent number 8,726,223
- Issue date May 13, 2014
- Atmel Corporation
- Sylvain Garnier
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Systems And Methods For Integrity Checking Of Code Or Data In A Mix...
- Publication number 20190057044
- Publication date Feb 21, 2019
- MICROCHIP TECHNOLOGY INCORPORATED
- Laurent Le Goffic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY EMULATION MECHANISM
- Publication number 20180046582
- Publication date Feb 15, 2018
- ATMEL CORPORATION
- Frode Milch Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATING DIGITAL DISPLAY
- Publication number 20140089537
- Publication date Mar 27, 2014
- Sebastien Jouin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIFURCATED PROCESSOR CHIP RESET ARCHITECTURES
- Publication number 20140089648
- Publication date Mar 27, 2014
- Atmel Corporation
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOT-PLUGGING DEBUGGER ARCHITECTURES
- Publication number 20140089748
- Publication date Mar 27, 2014
- Sylvain Garnier
- G01 - MEASURING TESTING
Information Patent Application
Method of optimising writing by a master block into a fifo type int...
- Publication number 20070255911
- Publication date Nov 1, 2007
- Atmel Nantes S.A.
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reverse polish notation device for handling tables, and electronic...
- Publication number 20070226461
- Publication date Sep 27, 2007
- Atmel Nantes SA
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reverse polish notation processing device, and electronic integrate...
- Publication number 20070192569
- Publication date Aug 16, 2007
- Atmel Nantes SA
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIFO-type one-way interfacing device between a master unit and a sl...
- Publication number 20070033306
- Publication date Feb 8, 2007
- Atmel Nantes SA
- Sylvain Garnier
- G06 - COMPUTING CALCULATING COUNTING

Sylvain Garnier

Person

Patents Grantslast 30 patents

Systems and methods for integrity checking of code or data in a mix...

Memory emulation mechanism

Processor maintaining reset-state after reset signal is suspended

Automating digital display

Hot-plugging debugger architectures

Patents Applicationslast 30 patents

Systems And Methods For Integrity Checking Of Code Or Data In A Mix...

MEMORY EMULATION MECHANISM

AUTOMATING DIGITAL DISPLAY

BIFURCATED PROCESSOR CHIP RESET ARCHITECTURES

HOT-PLUGGING DEBUGGER ARCHITECTURES

Method of optimising writing by a master block into a fifo type int...

Reverse polish notation device for handling tables, and electronic...

Reverse polish notation processing device, and electronic integrate...

FIFO-type one-way interfacing device between a master unit and a sl...