Szuya S. LIAO

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Confined epitaxial regions for semiconductor devices
- Patent number 12,094,955
- Issue date Sep 17, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source or drain structures with high germanium concentration cappin...
- Patent number 12,027,417
- Issue date Jul 2, 2024
- Intel Corporation
- Cory Bomberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor having a gate dielectric with a dipole laye...
- Patent number 11,984,506
- Issue date May 14, 2024
- Intel Corporation
- Vishal Tiwari
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor with a hybrid gate spacer including a low-k...
- Patent number 11,908,940
- Issue date Feb 20, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin shaping and integrated circuit structures resulting therefrom
- Patent number 11,901,457
- Issue date Feb 13, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mid-processing removal of semiconductor fins during fabrication of...
- Patent number 11,887,860
- Issue date Jan 30, 2024
- Intel Corporation
- Mehmet O. Baykan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architectures without fin end gap
- Patent number 11,869,889
- Issue date Jan 9, 2024
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device structures and double-sided electrical te...
- Patent number 11,854,894
- Issue date Dec 26, 2023
- Intel Corporation
- Valluri R. Rao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact architecture for capacitance reduction and satisfactory con...
- Patent number 11,824,097
- Issue date Nov 21, 2023
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual self-aligned gate endcap (SAGE) architectures
- Patent number 11,688,792
- Issue date Jun 27, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Confined epitaxial regions for semiconductor devices and methods of...
- Patent number 11,640,988
- Issue date May 2, 2023
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Unidirectional self-aligned gate endcap (SAGE) architectures with g...
- Patent number 11,605,632
- Issue date Mar 14, 2023
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge trigate and finFET devices
- Patent number 11,581,315
- Issue date Feb 14, 2023
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge and local interconnect
- Patent number 11,563,081
- Issue date Jan 24, 2023
- Daedalus Prime LLC
- Milton Clair Webb
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective gate spacers for semiconductor devices
- Patent number 11,532,724
- Issue date Dec 20, 2022
- Intel Corporation
- Scott B. Clendenning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge architecture with alternate channel material
- Patent number 11,456,357
- Issue date Sep 27, 2022
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having endcap plugs
- Patent number 11,329,138
- Issue date May 10, 2022
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact architecture for capacitance reduction and satisfactory con...
- Patent number 11,282,930
- Issue date Mar 22, 2022
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of doping fin structures of non-planar transistor devices
- Patent number 11,264,453
- Issue date Mar 1, 2022
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of doping fin structures of non-planar transistor devices
- Patent number 11,222,947
- Issue date Jan 11, 2022
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Unidirectional self-aligned gate endcap (SAGE) architectures with g...
- Patent number 11,217,582
- Issue date Jan 4, 2022
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual self-aligned gate endcap (SAGE) architectures
- Patent number 11,205,708
- Issue date Dec 21, 2021
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor with a hybrid gate spacer including a low-k...
- Patent number 11,183,592
- Issue date Nov 23, 2021
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor layer between source/drain regions and gate spacers
- Patent number 11,152,461
- Issue date Oct 19, 2021
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Confined epitaxial regions for semiconductor devices and methods of...
- Patent number 11,127,841
- Issue date Sep 21, 2021
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors employing non-selective deposition of source/drain mate...
- Patent number 11,101,268
- Issue date Aug 24, 2021
- Intel Corporation
- Karthik Jambunathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor nanowire device having cavity spacer and method of fa...
- Patent number 11,094,831
- Issue date Aug 17, 2021
- Intel Corporation
- Rishabh Mehandru
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dense memory arrays utilizing access transistors with back-side con...
- Patent number 11,056,492
- Issue date Jul 6, 2021
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate edge trigate and finFET devices
- Patent number 11,043,492
- Issue date Jun 22, 2021
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for increasing channel region tensile strain in n-MOS de...
- Patent number 11,011,620
- Issue date May 18, 2021
- Intel Corporation
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...
- Publication number 20240194533
- Publication date Jun 13, 2024
- Intel Corporation
- Valluri R. RAO
- G01 - MEASURING TESTING
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
- Publication number 20240088143
- Publication date Mar 14, 2024
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...
- Publication number 20240038857
- Publication date Feb 1, 2024
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF...
- Publication number 20230343599
- Publication date Oct 26, 2023
- Intel Corporation
- Mehmet O. Baykan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF...
- Publication number 20230215934
- Publication date Jul 6, 2023
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT
- Publication number 20230178594
- Publication date Jun 8, 2023
- Milton Clair Webb
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20230131126
- Publication date Apr 27, 2023
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP
- Publication number 20220310818
- Publication date Sep 29, 2022
- Intel Corporation
- Seung Hoon SUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...
- Publication number 20220165855
- Publication date May 26, 2022
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTU...
- Publication number 20220102554
- Publication date Mar 31, 2022
- Intel Corporation
- Jeremy J. GUTTMAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GROWTH SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH...
- Publication number 20220093590
- Publication date Mar 24, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES
- Publication number 20220077302
- Publication date Mar 10, 2022
- Intel Corporation
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K...
- Publication number 20220077311
- Publication date Mar 10, 2022
- Intel Corporation
- Szuya S. Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...
- Publication number 20220077145
- Publication date Mar 10, 2022
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYE...
- Publication number 20210408282
- Publication date Dec 30, 2021
- Intel Corporation
- Vishal TIWARI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH HIGH GERMANIUM CONCENTRATION CAPPIN...
- Publication number 20210407851
- Publication date Dec 30, 2021
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE OR DRAIN STRUCTURES WITH HIGH SURFACE GERMANIUM CONCENTRATION
- Publication number 20210408275
- Publication date Dec 30, 2021
- Intel Corporation
- Cory BOMBERGER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF...
- Publication number 20210359110
- Publication date Nov 18, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES
- Publication number 20210249411
- Publication date Aug 12, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...
- Publication number 20210193666
- Publication date Jun 24, 2021
- Intel Corporation
- Wilfred Gomes
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...
- Publication number 20210175124
- Publication date Jun 10, 2021
- Intel Corporation
- Valluri R. RAO
- G01 - MEASURING TESTING
Information Patent Application
FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM
- Publication number 20210167209
- Publication date Jun 3, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES
- Publication number 20210143265
- Publication date May 13, 2021
- Intel Corporation
- Scott B. CLENDENNING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP
- Publication number 20210091075
- Publication date Mar 25, 2021
- Intel Corporation
- Szuya S. LIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...
- Publication number 20210050423
- Publication date Feb 18, 2021
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT
- Publication number 20200388675
- Publication date Dec 10, 2020
- Intel Corporation
- Milton Clair WEBB
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...
- Publication number 20200287022
- Publication date Sep 10, 2020
- Intel Corporation
- Van H. LE
- B82 - NANO-TECHNOLOGY
Information Patent Application
MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF...
- Publication number 20200227267
- Publication date Jul 16, 2020
- Intel Corporation
- Mehmet O. Baykan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL TO SOURCE/DRAIN CONTACT AREA USING THIN NUCLEATION LAYER AND...
- Publication number 20200161440
- Publication date May 21, 2020
- Intel Corporation
- Ritesh Jhaveri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...
- Publication number 20200066851
- Publication date Feb 27, 2020
- Intel Corporation
- Rishabh MEHANDRU
- H01 - BASIC ELECTRIC ELEMENTS

Szuya S. LIAO

Person

Patents Grantslast 30 patents

Confined epitaxial regions for semiconductor devices

Source or drain structures with high germanium concentration cappin...

Field effect transistor having a gate dielectric with a dipole laye...

Field effect transistor with a hybrid gate spacer including a low-k...

Fin shaping and integrated circuit structures resulting therefrom

Mid-processing removal of semiconductor fins during fabrication of...

Self-aligned gate endcap (SAGE) architectures without fin end gap

Integrated circuit device structures and double-sided electrical te...

Contact architecture for capacitance reduction and satisfactory con...

Dual self-aligned gate endcap (SAGE) architectures

Confined epitaxial regions for semiconductor devices and methods of...

Unidirectional self-aligned gate endcap (SAGE) architectures with g...

Self-aligned gate edge trigate and finFET devices

Self-aligned gate edge and local interconnect

Selective gate spacers for semiconductor devices

Self-aligned gate edge architecture with alternate channel material

Self-aligned gate endcap (SAGE) architecture having endcap plugs

Contact architecture for capacitance reduction and satisfactory con...

Methods of doping fin structures of non-planar transistor devices

Methods of doping fin structures of non-planar transistor devices

Unidirectional self-aligned gate endcap (SAGE) architectures with g...

Dual self-aligned gate endcap (SAGE) architectures

Field effect transistor with a hybrid gate spacer including a low-k...

Semiconductor layer between source/drain regions and gate spacers

Confined epitaxial regions for semiconductor devices and methods of...

Transistors employing non-selective deposition of source/drain mate...

Semiconductor nanowire device having cavity spacer and method of fa...

Dense memory arrays utilizing access transistors with back-side con...

Self-aligned gate edge trigate and finFET devices

Techniques for increasing channel region tensile strain in n-MOS de...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...

MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF...

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF...

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT

FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP

CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...

GATE AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTU...

SELECTIVE GROWTH SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH...

DUAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES

FIELD EFFECT TRANSISTOR WITH A HYBRID GATE SPACER INCLUDING A LOW-K...

UNIDIRECTIONAL SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH G...

FIELD EFFECT TRANSISTOR HAVING A GATE DIELECTRIC WITH A DIPOLE LAYE...

SOURCE OR DRAIN STRUCTURES WITH HIGH GERMANIUM CONCENTRATION CAPPIN...

SOURCE OR DRAIN STRUCTURES WITH HIGH SURFACE GERMANIUM CONCENTRATION

CONFINED EPITAXIAL REGIONS FOR SEMICONDUCTOR DEVICES AND METHODS OF...

SELF-ALIGNED GATE EDGE TRIGATE AND FINFET DEVICES

DENSE MEMORY ARRAYS UTILIZING ACCESS TRANSISTORS WITH BACK-SIDE CON...

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...

FIN SHAPING AND INTEGRATED CIRCUIT STRUCTURES RESULTING THEREFROM

SELECTIVE GATE SPACERS FOR SEMICONDUCTOR DEVICES

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITHOUT FIN END GAP

CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...

SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT

FABRICATION OF MULTI-CHANNEL NANOWIRE DEVICES WITH SELF-ALIGNED INT...

MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF...

METAL TO SOURCE/DRAIN CONTACT AREA USING THIN NUCLEATION LAYER AND...

CONTACT ARCHITECTURE FOR CAPACITANCE REDUCTION AND SATISFACTORY CON...