Taarinya POLEPEDDI

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Saratoga, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,719,443
- Issue date Jul 21, 2020
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel that supports near memory and far memory access
- Patent number 10,691,626
- Issue date Jun 23, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel that supports near memory and far memory access
- Patent number 10,282,323
- Issue date May 7, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a multi-level memory hierarchy
- Patent number 10,241,912
- Issue date Mar 26, 2019
- Intel Corporation
- Raj K. Ramanujan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory channel that supports near memory and far memory access
- Patent number 10,241,943
- Issue date Mar 26, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
- Publication number 20190332556
- Publication date Oct 31, 2019
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20190220406
- Publication date Jul 18, 2019
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
- Publication number 20190018809
- Publication date Jan 17, 2019
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS
- Publication number 20180189207
- Publication date Jul 5, 2018
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20170249250
- Publication date Aug 31, 2017
- Intel Corporation
- Raj K. RAMANUJAN
- G06 - COMPUTING CALCULATING COUNTING