Tad J. Wilder

Person

South Hero, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methodology to prevent metal lines from current pulse damage
- Patent number 10,216,870
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Jeanne P. S. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Critical path delay prediction
- Patent number 10,169,500
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Margaret R. Charlebois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip performance monitoring system and method
- Patent number 10,006,964
- Issue date Jun 26, 2018
- International Business Machines Corporation
- Margaret R. Charlebois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Burn-in power performance optimization
- Patent number 9,940,430
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit chip reliability qualification using a sample-sp...
- Patent number 9,891,275
- Issue date Feb 13, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G05 - CONTROLLING REGULATING
Information Patent Grant
On-chip usable life depletion meter and associated method
- Patent number 9,791,502
- Issue date Oct 17, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit chip reliability using reliability-optimized fai...
- Patent number 9,639,645
- Issue date May 2, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for identifying operating temperatures and modify...
- Patent number 9,625,325
- Issue date Apr 18, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods to prevent incorporation of a used integrated c...
- Patent number 9,618,566
- Issue date Apr 11, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reliability-optimized selective voltage binning
- Patent number 9,489,482
- Issue date Nov 8, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip performance monitoring system and method
- Patent number 9,383,766
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Grant
Flexible performance screen ring oscillator within a scan chain
- Patent number 9,188,643
- Issue date Nov 17, 2015
- GLOBALFOUNDRIES Inc.
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Grant
Adaptive power control using timing canonicals
- Patent number 9,157,956
- Issue date Oct 13, 2015
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Performance screen ring oscillator formed from paired scan chains
- Patent number 9,128,151
- Issue date Sep 8, 2015
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Grant
Performance screen ring oscillator formed from multi-dimensional pa...
- Patent number 9,097,765
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Grant
Ring oscillator
- Patent number 8,754,696
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Margaret R. Charlebois
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit design using design variable function slope sensitivity
- Patent number 8,464,199
- Issue date Jun 11, 2013
- International Business Machines Corporation
- Margaret R. Charlebois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for increased effectiveness of delay and trans...
- Patent number 8,381,050
- Issue date Feb 19, 2013
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor layer forming method and structure
- Patent number 8,341,588
- Issue date Dec 25, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system to optimize semiconductor products for power, per...
- Patent number 8,302,063
- Issue date Oct 30, 2012
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for identifying and implementing flexible logic block logic...
- Patent number 8,181,148
- Issue date May 15, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for identifying and implementing flexible logic block log...
- Patent number 8,141,028
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip design and fabrication method optimized for profit
- Patent number 8,086,988
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Nathan Buck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing impact of design changes for integrated circuit designs
- Patent number 8,060,845
- Issue date Nov 15, 2011
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LSSD-compatible edge-triggered shift register latch
- Patent number 7,543,203
- Issue date Jun 2, 2009
- International Business Machines Corporation
- Gerry Ashton
- G01 - MEASURING TESTING
Information Patent Grant
Design structure for facilitating engineering changes in integrated...
- Patent number 7,480,888
- Issue date Jan 20, 2009
- International Business Machines Corporation
- Clarence Rosser Ogilvie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial good integrated circuit and method of testing same
- Patent number 7,478,301
- Issue date Jan 13, 2009
- International Business Machines Corporation
- Leonard O. Farnsworth, III
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial good integrated circuit and method of testing same
- Patent number 7,434,129
- Issue date Oct 7, 2008
- International Business Machines Corporation
- Leonard O. Farnsworth, III
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial good integrated circuit and method of testing same
- Patent number 7,305,600
- Issue date Dec 4, 2007
- International Business Machines Corporation
- Leonard O. Farnsworth, III
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for performing shapes correction of a multi-cell...
- Patent number 7,302,673
- Issue date Nov 27, 2007
- International Business Machines Corporation
- Peter Anton Habitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...
- Publication number 20180052201
- Publication date Feb 22, 2018
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILIT...
- Publication number 20170212165
- Publication date Jul 27, 2017
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
METHODOLOGY TO PREVENT METAL LINES FROM CURRENT PULSE DAMAGE
- Publication number 20170199949
- Publication date Jul 13, 2017
- International Business Machines Corporation
- JEANNE P. S. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BURN-IN POWER PERFORMANCE OPTIMIZATION
- Publication number 20170161426
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...
- Publication number 20160377674
- Publication date Dec 29, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAI...
- Publication number 20160371413
- Publication date Dec 22, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD
- Publication number 20160320214
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED C...
- Publication number 20160238653
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFY...
- Publication number 20160240479
- Publication date Aug 18, 2016
- GLOBALFOUNDRIES INC.
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
CHIP PERFORMANCE MONITORING SYSTEM AND METHOD
- Publication number 20160231379
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Application
CHIP PERFORMANCE MONITORING SYSTEM AND METHOD
- Publication number 20140195196
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Application
FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN
- Publication number 20140132290
- Publication date May 15, 2014
- International Business Machines Corporation
- Margaret R. Charlebois
- G01 - MEASURING TESTING
Information Patent Application
ADAPTIVE POWER CONTROL USING TIMING CANONICALS
- Publication number 20140074422
- Publication date Mar 13, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
RING OSCILLATOR
- Publication number 20140028365
- Publication date Jan 30, 2014
- International Business Machines Corporation
- Margaret R. Charlebois
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CRITICAL PATH DELAY PREDICTION
- Publication number 20130041608
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Margaret R. Charlebois
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC B...
- Publication number 20120167022
- Publication date Jun 28, 2012
- International Business Machines Corporation
- Robert D. HERZL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE
- Publication number 20120083913
- Publication date Apr 5, 2012
- International Business Machines Corporation
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM TO OPTIMIZE SEMICONDUCTOR PRODUCTS FOR POWER, PER...
- Publication number 20110288829
- Publication date Nov 24, 2011
- International Business Machines Corporation
- Jeanne P. BICKFORD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR INCREASED EFFECTIVENESS OF DELAY AND TRANS...
- Publication number 20110121838
- Publication date May 26, 2011
- International Business Machines Corporation
- Pamela S. Gillis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT
- Publication number 20100293512
- Publication date Nov 18, 2010
- International Business Machines Corporation
- Nathan Buck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Minimizing Impact of Design Changes For Integrated Circu...
- Publication number 20100017773
- Publication date Jan 21, 2010
- International Business Machines Corporation
- Robert D. HERZL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BL...
- Publication number 20090183134
- Publication date Jul 16, 2009
- International Business Machines Corporation
- Robert D. HERZL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Device for Identifying and Implementing Flexible Logic B...
- Publication number 20090183135
- Publication date Jul 16, 2009
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE EN...
- Publication number 20090045839
- Publication date Feb 19, 2009
- International Business Machines Corporation
- Robert D. HERZL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE EN...
- Publication number 20090045836
- Publication date Feb 19, 2009
- Robert D. Herzl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME
- Publication number 20080209289
- Publication date Aug 28, 2008
- Leonard O. Farnsworth
- G01 - MEASURING TESTING
Information Patent Application
PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME
- Publication number 20080010571
- Publication date Jan 10, 2008
- Leonard O. Farnsworth
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION
- Publication number 20070061771
- Publication date Mar 15, 2007
- International Business Machines Corporation
- Peter Anton Habitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
LSSD-COMPATIBLE EDGE-TRIGGERED SHIFT REGISTER LATCH
- Publication number 20050204244
- Publication date Sep 15, 2005
- International Business Machines Corporation
- Gerry Ashton
- G01 - MEASURING TESTING
Information Patent Application
Partial good integrated circuit and method of testing same
- Publication number 20050047224
- Publication date Mar 3, 2005
- International Business Machines Corporation
- Leonard O. Farnsworth
- G01 - MEASURING TESTING

Tad J. Wilder

Person

Patents Grantslast 30 patents

Methodology to prevent metal lines from current pulse damage

Critical path delay prediction

Chip performance monitoring system and method

Burn-in power performance optimization

Integrated circuit chip reliability qualification using a sample-sp...

On-chip usable life depletion meter and associated method

Integrated circuit chip reliability using reliability-optimized fai...

System and method for identifying operating temperatures and modify...

Systems and methods to prevent incorporation of a used integrated c...

Reliability-optimized selective voltage binning

Chip performance monitoring system and method

Flexible performance screen ring oscillator within a scan chain

Adaptive power control using timing canonicals

Performance screen ring oscillator formed from paired scan chains

Performance screen ring oscillator formed from multi-dimensional pa...

Ring oscillator

Circuit design using design variable function slope sensitivity

Method and apparatus for increased effectiveness of delay and trans...

Semiconductor layer forming method and structure

Method and system to optimize semiconductor products for power, per...

Method for identifying and implementing flexible logic block logic...

Structure for identifying and implementing flexible logic block log...

Chip design and fabrication method optimized for profit

Minimizing impact of design changes for integrated circuit designs

LSSD-compatible edge-triggered shift register latch

Design structure for facilitating engineering changes in integrated...

Partial good integrated circuit and method of testing same

Partial good integrated circuit and method of testing same

Partial good integrated circuit and method of testing same

Method and system for performing shapes correction of a multi-cell...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...

RESISTANCE MEASUREMENT-DEPENDENT INTEGRATED CIRCUIT CHIP RELIABILIT...

METHODOLOGY TO PREVENT METAL LINES FROM CURRENT PULSE DAMAGE

BURN-IN POWER PERFORMANCE OPTIMIZATION

INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SP...

INTEGRATED CIRCUIT CHIP RELIABILITY USING RELIABILITY-OPTIMIZED FAI...

ON-CHIP USABLE LIFE DEPLETION METER AND ASSOCIATED METHOD

SYSTEMS AND METHODS TO PREVENT INCORPORATION OF A USED INTEGRATED C...

SYSTEM AND METHOD FOR IDENTIFYING OPERATING TEMPERATURES AND MODIFY...

CHIP PERFORMANCE MONITORING SYSTEM AND METHOD

CHIP PERFORMANCE MONITORING SYSTEM AND METHOD

FLEXIBLE PERFORMANCE SCREEN RING OSCILLATOR WITHIN A SCAN CHAIN

ADAPTIVE POWER CONTROL USING TIMING CANONICALS

RING OSCILLATOR

CRITICAL PATH DELAY PREDICTION

METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC B...

SEMICONDUCTOR LAYER FORMING METHOD AND STRUCTURE

METHOD AND SYSTEM TO OPTIMIZE SEMICONDUCTOR PRODUCTS FOR POWER, PER...

METHOD AND APPARATUS FOR INCREASED EFFECTIVENESS OF DELAY AND TRANS...

CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT

Method for Minimizing Impact of Design Changes For Integrated Circu...

DESIGN STRUCTURE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BL...

Method and Device for Identifying and Implementing Flexible Logic B...

ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE EN...

ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE EN...

PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME

PARTIAL GOOD INTEGRATED CIRCUIT AND METHOD OF TESTING SAME

METHOD FOR RETICLE SHAPES ANALYSIS AND CORRECTION

LSSD-COMPATIBLE EDGE-TRIGGERED SHIFT REGISTER LATCH

Partial good integrated circuit and method of testing same