Tad Kwasniewski

Person

Ottawa, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 8,217,693
- Issue date Jul 10, 2012
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Blind adaptive decision feedback equalizer for high-speed serial co...
- Patent number 8,098,588
- Issue date Jan 17, 2012
- Altera Corporation
- Charles E. Berndt
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Zero-delay serial communications circuitry for serial interconnects
- Patent number 8,014,480
- Issue date Sep 6, 2011
- Altera Corporation
- Jingcheng Zhuang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fractional delay-locked loops
- Patent number 7,940,098
- Issue date May 10, 2011
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 7,902,888
- Issue date Mar 8, 2011
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-adjusted pre-emphasis and equalization for data communication
- Patent number 7,848,402
- Issue date Dec 7, 2010
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Frequency synthesizer circuitry employing delay line
- Patent number 7,843,275
- Issue date Nov 30, 2010
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for equalization in high-speed backplane data...
- Patent number 7,697,603
- Issue date Apr 13, 2010
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for simulating link performance
- Patent number 7,693,691
- Issue date Apr 6, 2010
- Altera Corporation
- Yuming Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fractional delay-locked loops
- Patent number 7,675,332
- Issue date Mar 9, 2010
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for all-digital serializer-de-serializer and associated m...
- Patent number 7,656,323
- Issue date Feb 2, 2010
- Altera Corporation
- William W. Bereza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital loop circuit for programmable logic device
- Patent number 7,633,322
- Issue date Dec 15, 2009
- Altera Corporation
- Jingcheng Zhuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-mode LVDS/CML transmitter methods and apparatus
- Patent number 7,598,779
- Issue date Oct 6, 2009
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock data recovery loop with separate proportional path
- Patent number 7,580,497
- Issue date Aug 25, 2009
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multitap fractional baud period pre-emphasis for data transmission
- Patent number 7,528,635
- Issue date May 5, 2009
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of clock signal with data signal
- Patent number 7,486,752
- Issue date Feb 3, 2009
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Capacitance switch circuitry for digitally controlled oscillators
- Patent number 7,474,167
- Issue date Jan 6, 2009
- Altera Corporation
- Jingcheng Zhuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage controlled oscillator circuitry and methods
- Patent number 7,414,484
- Issue date Aug 19, 2008
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for wide tuning-range ring oscillators
- Patent number 7,388,443
- Issue date Jun 17, 2008
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 7,385,429
- Issue date Jun 10, 2008
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive communication methods and apparatus
- Patent number 7,239,849
- Issue date Jul 3, 2007
- Altera Corporation
- Bill Bereza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential signal detector methods and apparatus
- Patent number 7,224,191
- Issue date May 29, 2007
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multitap fractional baud period pre-emphasis for data transmission
- Patent number 7,196,557
- Issue date Mar 27, 2007
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential signal detector methods and apparatus
- Patent number 7,157,944
- Issue date Jan 2, 2007
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of recovered clock with data signal
- Patent number 7,143,312
- Issue date Nov 28, 2006
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and methods for wide tuning-range ring oscillators
- Patent number 7,061,334
- Issue date Jun 13, 2006
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Half-rate linear quardrature phase detector for clock recovery
- Patent number 6,970,020
- Issue date Nov 29, 2005
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pre-emphasis circuitry and methods
- Patent number 6,956,407
- Issue date Oct 18, 2005
- Altera Corporation
- Mashkoor Baig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
CHARGE PUMP WITH REDUCED CURRENT MISMATCH
- Publication number 20110156806
- Publication date Jun 30, 2011
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR TIME-DOMAIN PRE-EMPHASIS AND TIME-DOMAIN EQUALIZATION...
- Publication number 20100027607
- Publication date Feb 4, 2010
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEV...
- Publication number 20090302887
- Publication date Dec 10, 2009
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR ALL-DIGITAL SERIALIZER-DE-SERIALIZER AND ASSOCIATED M...
- Publication number 20080298476
- Publication date Dec 4, 2008
- William W. Bereza
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multitap fractional baud period pre-emphasis for data transmission
- Publication number 20070241795
- Publication date Oct 18, 2007
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Voltage controlled oscillator circuitry and methods
- Publication number 20070069831
- Publication date Mar 29, 2007
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock data recovery loop with separate proportional path
- Publication number 20070002993
- Publication date Jan 4, 2007
- ALTERA CORPORATION, a corporation of Delaware
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and methods for wide tuning-range ring oscillators
- Publication number 20060192623
- Publication date Aug 31, 2006
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input stage threshold adjustment for high speed data communications
- Publication number 20050160327
- Publication date Jul 21, 2005
- Altera Corporation
- Mashkoor Baig
- G01 - MEASURING TESTING
Information Patent Application
Pre-emphasis circuitry and methods
- Publication number 20050093580
- Publication date May 5, 2005
- Altera Corporation
- Mashkoor Baig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Adaptive communication methods and apparatus
- Publication number 20050095988
- Publication date May 5, 2005
- Altera Corporation
- Bill Bereza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Active peaking using differential pairs of transistors
- Publication number 20030141919
- Publication date Jul 31, 2003
- Shoujun Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Tad Kwasniewski

Person

Patents Grantslast 30 patents

Charge pump with reduced current mismatch

Blind adaptive decision feedback equalizer for high-speed serial co...

Zero-delay serial communications circuitry for serial interconnects

Fractional delay-locked loops

Charge pump with reduced current mismatch

Phase-adjusted pre-emphasis and equalization for data communication

Frequency synthesizer circuitry employing delay line

Methods and apparatus for equalization in high-speed backplane data...

Systems and methods for simulating link performance

Fractional delay-locked loops

Apparatus for all-digital serializer-de-serializer and associated m...

Digital loop circuit for programmable logic device

Dual-mode LVDS/CML transmitter methods and apparatus

Clock data recovery loop with separate proportional path

Multitap fractional baud period pre-emphasis for data transmission

Alignment of clock signal with data signal

Capacitance switch circuitry for digitally controlled oscillators

Voltage controlled oscillator circuitry and methods

Apparatus and method for wide tuning-range ring oscillators

Charge pump with reduced current mismatch

Adaptive communication methods and apparatus

Differential signal detector methods and apparatus

Multitap fractional baud period pre-emphasis for data transmission

Differential signal detector methods and apparatus

Alignment of recovered clock with data signal

Apparatus and methods for wide tuning-range ring oscillators

Half-rate linear quardrature phase detector for clock recovery

Pre-emphasis circuitry and methods

Patents Applicationslast 30 patents

CHARGE PUMP WITH REDUCED CURRENT MISMATCH

APPARATUS FOR TIME-DOMAIN PRE-EMPHASIS AND TIME-DOMAIN EQUALIZATION...

APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEV...

APPARATUS FOR ALL-DIGITAL SERIALIZER-DE-SERIALIZER AND ASSOCIATED M...

Multitap fractional baud period pre-emphasis for data transmission

Voltage controlled oscillator circuitry and methods

Clock data recovery loop with separate proportional path

Apparatus and methods for wide tuning-range ring oscillators

Input stage threshold adjustment for high speed data communications

Pre-emphasis circuitry and methods

Adaptive communication methods and apparatus

Active peaking using differential pairs of transistors