Tadashi Tachibana

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Patents Grantslast 30 patents

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Semiconductor memory device having a back gate voltage controlled d...
- Patent number 6,034,920
- Issue date Mar 7, 2000
- Texas Instruments Incorporated
- Shunichi Sukegawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Matched delay word line strap
- Patent number 5,841,688
- Issue date Nov 24, 1998
- Texas Instruments Incorporated
- Shunichi Sukegawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,768,214
- Issue date Jun 16, 1998
- Texas Instruments Incorporated
- Ken Saitoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with built-in defective bit relief circuit
- Patent number 4,890,262
- Issue date Dec 26, 1989
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
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Semiconductor ROM with reduced supply voltage requirement
- Patent number 4,862,413
- Issue date Aug 29, 1989
- Texas Instruments Incorporated
- Masashi Hashimoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Self refresh circuitry for dynamic memory
- Patent number 4,653,030
- Issue date Mar 24, 1987
- Texas Instruments Incorporated
- Tadashi Tachibana
- G11 - INFORMATION STORAGE