Taewoo Lee

Person

Yongin-si, KR

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor die and method of forming Fo-WLCSP vertical interconn...
- Patent number 9,153,494
- Issue date Oct 6, 2015
- STATS ChipPAC, Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming non-linear interconnect...
- Patent number 9,117,812
- Issue date Aug 25, 2015
- STATS ChipPAC, Ltd.
- JaeHyun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with posts and method of manufa...
- Patent number 9,082,887
- Issue date Jul 14, 2015
- Stats Chippac Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die and method of forming Fo-WLCSP vertical interconn...
- Patent number 8,895,440
- Issue date Nov 25, 2014
- STATS ChipPAC, Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with thermal dispersal structur...
- Patent number 8,692,365
- Issue date Apr 8, 2014
- Stats Chippac Ltd.
- DongSoo Moon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming non-linear interconnect...
- Patent number 8,642,384
- Issue date Feb 4, 2014
- STATS ChipPAC, Ltd.
- JaeHyun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with an interposer and method o...
- Patent number 8,624,370
- Issue date Jan 7, 2014
- Stats Chippac Ltd.
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and method of forming electrical interconnecti...
- Patent number 8,574,964
- Issue date Nov 5, 2013
- STATS ChipPAC, Ltd.
- SungWon Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with vertical interconnection a...
- Patent number 8,502,387
- Issue date Aug 6, 2013
- Stats Chippac Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with cavity and method of manuf...
- Patent number 8,390,110
- Issue date Mar 5, 2013
- Stats Chippac Ltd.
- Sang-Ho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package system with via z-interconnections and method fo...
- Patent number 8,258,008
- Issue date Sep 4, 2012
- Stats Chippac Ltd.
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging system with interconnect and method of...
- Patent number 8,115,293
- Issue date Feb 14, 2012
- Stats Chippac Ltd.
- DongSoo Moon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grooving bumped wafer pre-underfill system
- Patent number 8,030,769
- Issue date Oct 4, 2011
- STATS ChipPAC, Ltd.
- Junghoon Shin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer system with partial cuts
- Patent number 8,017,502
- Issue date Sep 13, 2011
- Stats Chippac Ltd.
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package-on-package system with via Z-interconnections
- Patent number 7,863,755
- Issue date Jan 4, 2011
- Stats Chippac Ltd.
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with wafer trimming
- Patent number 7,786,551
- Issue date Aug 31, 2010
- Stats Chippac Ltd.
- Seung Wook Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Grooving bumped wafer pre-underfill system
- Patent number 7,727,875
- Issue date Jun 1, 2010
- STATS ChipPAC, Ltd.
- Junghoon Shin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system with a debris trapping system
- Patent number 7,659,140
- Issue date Feb 9, 2010
- Stats Chippac Ltd.
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...
- Publication number 20150357274
- Publication date Dec 10, 2015
- STATS ChipPAC, Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Non-Linear Interconnect...
- Publication number 20140103503
- Publication date Apr 17, 2014
- STATS ChipPAC, Ltd.
- JaeHyun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Electrical Interconnecti...
- Publication number 20140008783
- Publication date Jan 9, 2014
- STATS ChipPAC, Ltd.
- SungWon Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...
- Publication number 20130299973
- Publication date Nov 14, 2013
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Non-Linear Interconnect...
- Publication number 20130234318
- Publication date Sep 12, 2013
- STATS ChipPAC, Ltd.
- JaeHyun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTUR...
- Publication number 20120319267
- Publication date Dec 20, 2012
- DongSoo Moon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION A...
- Publication number 20120146235
- Publication date Jun 14, 2012
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...
- Publication number 20120032340
- Publication date Feb 9, 2012
- STATS ChipPAC, Ltd.
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFA...
- Publication number 20110291264
- Publication date Dec 1, 2011
- DaeSik Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device and Method of Forming Electrical Interconnecti...
- Publication number 20110254146
- Publication date Oct 20, 2011
- STATS ChipPAC, Ltd.
- SungWon Cho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...
- Publication number 20110133325
- Publication date Jun 9, 2011
- DongSoo Moon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUF...
- Publication number 20110089554
- Publication date Apr 21, 2011
- Sang-Ho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FO...
- Publication number 20110084401
- Publication date Apr 14, 2011
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND...
- Publication number 20100237481
- Publication date Sep 23, 2010
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD O...
- Publication number 20100237483
- Publication date Sep 23, 2010
- HeeJo Chi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Grooving Bumped Wafer Pre-Underfill System
- Publication number 20100200986
- Publication date Aug 12, 2010
- STATS ChipPAC, Ltd.
- Junghoon SHIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS
- Publication number 20090236752
- Publication date Sep 24, 2009
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH STACKING VIA INTE...
- Publication number 20090140408
- Publication date Jun 4, 2009
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Grooving Bumped Wafer Pre-Underfill System
- Publication number 20080318396
- Publication date Dec 25, 2008
- STATS ChipPAC, Ltd.
- Junghoon SHIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH A DEBRIS TRAPPING SYSTEM
- Publication number 20080242053
- Publication date Oct 2, 2008
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER SYSTEM WITH PARTIAL CUTS
- Publication number 20080153262
- Publication date Jun 26, 2008
- STATS ChipPAC Ltd.
- Taewoo Lee
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Semiconductor die and method of forming Fo-WLCSP vertical interconn...

Semiconductor device and method of forming non-linear interconnect...

Integrated circuit packaging system with posts and method of manufa...

Semiconductor die and method of forming Fo-WLCSP vertical interconn...

Integrated circuit packaging system with thermal dispersal structur...

Semiconductor device and method of forming non-linear interconnect...

Integrated circuit packaging system with an interposer and method o...

Semiconductor device and method of forming electrical interconnecti...

Integrated circuit packaging system with vertical interconnection a...

Integrated circuit packaging system with cavity and method of manuf...

Package-on-package system with via z-interconnections and method fo...

Integrated circuit packaging system with interconnect and method of...

Grooving bumped wafer pre-underfill system

Wafer system with partial cuts

Package-on-package system with via Z-interconnections

Integrated circuit system with wafer trimming

Grooving bumped wafer pre-underfill system

Integrated circuit system with a debris trapping system

Patents Applicationslast 30 patents

Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...

Semiconductor Device and Method of Forming Non-Linear Interconnect...

Semiconductor Device and Method of Forming Electrical Interconnecti...

Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...

Semiconductor Device and Method of Forming Non-Linear Interconnect...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THERMAL DISPERSAL STRUCTUR...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION A...

Semiconductor Die and Method of Forming FO-WLCSP Vertical Interconn...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POSTS AND METHOD OF MANUFA...

Semiconductor Device and Method of Forming Electrical Interconnecti...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CAVITY AND METHOD OF MANUF...

PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS AND METHOD FO...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL SIDED CONNECTION AND...

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERPOSER AND METHOD O...

Grooving Bumped Wafer Pre-Underfill System

PACKAGE-ON-PACKAGE SYSTEM WITH VIA Z-INTERCONNECTIONS

INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH STACKING VIA INTE...

Grooving Bumped Wafer Pre-Underfill System

INTEGRATED CIRCUIT SYSTEM WITH A DEBRIS TRAPPING SYSTEM

WAFER SYSTEM WITH PARTIAL CUTS