TREA

Tai Hirakawa

Follow

Person

  • Hiroshima-shi, JP
People

Patents Grantslast 30 patents

  • Information Patent Grant

    Multi-port integrated cache
    • Patent number 7,694,077
    • Issue date Apr 6, 2010
    • Semiconductor Technology Academic Research Center
    • Tetsuo Hironaka
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Grant

    Multi-port integrated cache
    • Patent number 7,360,024
    • Issue date Apr 15, 2008
    • Semiconductor Technology Academic Research Center
    • Tetsuo Hironaka
    • G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

  • Information Patent Application

    MULTI-PORT INTEGRATED CACHE
    • Publication number 20080222360
    • Publication date Sep 11, 2008
    • Semiconductor Technology Academic Research Center
    • Tetsuo Hironaka
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    Multi-port integrated cache
    • Publication number 20040088489
    • Publication date May 6, 2004
    • Semiconductor Technology Academic Research Center
    • Tetsuo Hironaka
    • G06 - COMPUTING CALCULATING COUNTING