Tak Kwong Wong

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Overvoltage protection circuits and methods of operating same
- Patent number 9,793,708
- Issue date Oct 17, 2017
- Integrated Device Technology, Inc.
- Alan Wolfram Glaser
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Systems and methods for power management in electronic devices
- Patent number 8,892,930
- Issue date Nov 18, 2014
- Integrated Device Technology Inc.
- Tzong-Kwang Henry Yeh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Systems and methods for monitoring and controlling binary state dev...
- Patent number 7,904,667
- Issue date Mar 8, 2011
- Integrated Device Technology, Inc.
- Yunsheng Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Input termination for delay locked loop feedback with impedance mat...
- Patent number 7,898,288
- Issue date Mar 1, 2011
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for monitoring and controlling binary state dev...
- Patent number 7,747,828
- Issue date Jun 29, 2010
- Integrated Device Technology, Inc.
- Yunsheng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Impedance matching logic
- Patent number 7,688,105
- Issue date Mar 30, 2010
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Using a delay clock to optimize the timing margin of sequential logic
- Patent number 7,647,535
- Issue date Jan 12, 2010
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular distributive arithmetic logic unit
- Patent number 7,571,300
- Issue date Aug 4, 2009
- Integrated Device Technologies, inc.
- Tak Kwong Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing timing skew among chip level outputs for registered outp...
- Patent number 7,292,064
- Issue date Nov 6, 2007
- Integrated Device Technology, Inc.
- Tak Kwong (Dino) Wong
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain registers that utilize feedback paths within latch units...
- Patent number 7,162,673
- Issue date Jan 9, 2007
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- G01 - MEASURING TESTING
Information Patent Grant
ESD damage protection using a clamp circuit
- Patent number 6,069,782
- Issue date May 30, 2000
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR POWER MANAGEMENT IN ELECTRONIC DEVICES
- Publication number 20100031073
- Publication date Feb 4, 2010
- Tzong-Kwang Henry Yeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPEDANCE MATCHING LOGIC
- Publication number 20100007373
- Publication date Jan 14, 2010
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Modular Distributive Arithmetic Logic Unit
- Publication number 20080168256
- Publication date Jul 10, 2008
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using A Delay Clock To Optimize The Timing Margin Of Sequential Logic
- Publication number 20080143383
- Publication date Jun 19, 2008
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input Termination For Delay Locked Loop Feedback With Impedance Mat...
- Publication number 20080136443
- Publication date Jun 12, 2008
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MINIMIZING TIMING SKEW AMONG CHIP LEVEL OUTPUTS FOR REGISTERED OUTP...
- Publication number 20070236249
- Publication date Oct 11, 2007
- Integrated Device Technology, Inc.
- Tak Kwong (Dino) Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data Output Clock Selection Circuit For Quad-Data Rate Interface
- Publication number 20070234251
- Publication date Oct 4, 2007
- Integrated Device Technology, Inc.
- Tak Kwong (Dino) Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for monitoring and controlling binary state dev...
- Publication number 20060277372
- Publication date Dec 7, 2006
- Integrated Device Technology, Inc.
- Yunsheng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and methods for monitoring and controlling binary state dev...
- Publication number 20060106989
- Publication date May 18, 2006
- Yunsheng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Statistics engine
- Publication number 20060101152
- Publication date May 11, 2006
- Integrated Device Technology, Inc.
- Tzong-Kwang Yeh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bitline layout in a dual port memory array
- Publication number 20060092749
- Publication date May 4, 2006
- Integrated Device Technology, Inc.
- Tak Kwong Wong
- G11 - INFORMATION STORAGE
Information Patent Application
Scan chain registers that utilize feedback paths within latch units...
- Publication number 20050108604
- Publication date May 19, 2005
- Tak Kwong Wong
- G01 - MEASURING TESTING

Tak Kwong Wong

Person

Patents Grantslast 30 patents

Overvoltage protection circuits and methods of operating same

Systems and methods for power management in electronic devices

Systems and methods for monitoring and controlling binary state dev...

Input termination for delay locked loop feedback with impedance mat...

Systems and methods for monitoring and controlling binary state dev...

Impedance matching logic

Using a delay clock to optimize the timing margin of sequential logic

Modular distributive arithmetic logic unit

Minimizing timing skew among chip level outputs for registered outp...

Scan chain registers that utilize feedback paths within latch units...

ESD damage protection using a clamp circuit

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR POWER MANAGEMENT IN ELECTRONIC DEVICES

IMPEDANCE MATCHING LOGIC

Modular Distributive Arithmetic Logic Unit

Using A Delay Clock To Optimize The Timing Margin Of Sequential Logic

Input Termination For Delay Locked Loop Feedback With Impedance Mat...

MINIMIZING TIMING SKEW AMONG CHIP LEVEL OUTPUTS FOR REGISTERED OUTP...

Data Output Clock Selection Circuit For Quad-Data Rate Interface

Systems and methods for monitoring and controlling binary state dev...

Systems and methods for monitoring and controlling binary state dev...

Statistics engine

Bitline layout in a dual port memory array

Scan chain registers that utilize feedback paths within latch units...