Takaaki Nedachi

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked module, stacking method, cooling/feeding mechanism, and sta...
- Patent number 10,499,545
- Issue date Dec 3, 2019
- NEC Corporation
- Takaaki Nedachi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polyphase clock generator
- Patent number 8,803,583
- Issue date Aug 12, 2014
- NEC Corporation
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiphase clock generation circuit
- Patent number 8,169,247
- Issue date May 1, 2012
- NEC Corporation
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver circuit and receiver circuit testing method
- Patent number 7,860,472
- Issue date Dec 28, 2010
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor integrated circuit
- Patent number 7,791,382
- Issue date Sep 7, 2010
- NEC Corporation
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer circuit
- Patent number 7,378,877
- Issue date May 27, 2008
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Output buffer circuit having pre-emphasis function
- Patent number 7,164,299
- Issue date Jan 16, 2007
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Output buffer circuit
- Patent number 6,674,313
- Issue date Jan 6, 2004
- NEC Electronics Corporation
- Masakazu Kurisu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal transmission system
- Patent number 6,570,463
- Issue date May 27, 2003
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
STACKED MODULE, STACKING METHOD, COOLING/FEEDING MECHANISM, AND STA...
- Publication number 20180270992
- Publication date Sep 20, 2018
- NEC Corporation
- Takaaki Nedachi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
POLYPHASE CLOCK GENERATOR
- Publication number 20130049831
- Publication date Feb 28, 2013
- NEC Corporation
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPHASE CLOCK GENERATION CIRCUIT
- Publication number 20110102028
- Publication date May 5, 2011
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20090251186
- Publication date Oct 8, 2009
- Takaaki Nedachi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECEIVER CIRCUIT AND RECEIVER CIRCUIT TESTING METHOD
- Publication number 20070224958
- Publication date Sep 27, 2007
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Output buffer circuit
- Publication number 20060214691
- Publication date Sep 28, 2006
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Output buffer circuit having pre-emphasis function
- Publication number 20040145394
- Publication date Jul 29, 2004
- NEC Corporation
- Takaaki Nedachi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Output buffer circuit
- Publication number 20020030517
- Publication date Mar 14, 2002
- NEC Corporation
- Masakazu Kurisu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Takaaki Nedachi

Person

Patents Grantslast 30 patents

Stacked module, stacking method, cooling/feeding mechanism, and sta...

Polyphase clock generator

Multiphase clock generation circuit

Receiver circuit and receiver circuit testing method

Semiconductor integrated circuit

Output buffer circuit

Output buffer circuit having pre-emphasis function

Output buffer circuit

Signal transmission system

Patents Applicationslast 30 patents

STACKED MODULE, STACKING METHOD, COOLING/FEEDING MECHANISM, AND STA...

POLYPHASE CLOCK GENERATOR

MULTIPHASE CLOCK GENERATION CIRCUIT

SEMICONDUCTOR INTEGRATED CIRCUIT

RECEIVER CIRCUIT AND RECEIVER CIRCUIT TESTING METHOD

Output buffer circuit

Output buffer circuit having pre-emphasis function

Output buffer circuit