Takashi Mitsuhashi

Person

Fujisawa, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for stencil design for particle beam writing
- Patent number 8,533,640
- Issue date Sep 10, 2013
- D2S, Inc.
- Dmitri Lapanik
- B82 - NANO-TECHNOLOGY
Information Patent Grant
System and method of electron beam writing
- Patent number 8,525,135
- Issue date Sep 3, 2013
- Cadence Design Systems, Inc.
- Dmitri Lanpanik
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Cell projection charged particle beam lithography
- Patent number 8,426,832
- Issue date Apr 23, 2013
- D2S, Inc.
- Kenji Yoshida
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method and system for lithography simulation and measurement of cri...
- Patent number 8,364,452
- Issue date Jan 29, 2013
- Cadence Design Systems, Inc.
- Takashi Mitsuhashi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and system for lithography simulation and measurement of cri...
- Patent number 7,953,582
- Issue date May 31, 2011
- Cadence Design Systems, Inc.
- Daisuke Hara
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Stencil, stencil design system and method for cell projection parti...
- Patent number 7,914,954
- Issue date Mar 29, 2011
- D2S, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method and system for proximity effect and dose correction for a pa...
- Patent number 7,902,528
- Issue date Mar 8, 2011
- Cadence Design Systems, Inc.
- Daisuke Hara
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for optical proximity correction of a reticle to be manufact...
- Patent number 7,901,845
- Issue date Mar 8, 2011
- D2S, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method and system for improving particle beam lithography
- Patent number 7,897,522
- Issue date Mar 1, 2011
- Cadence Design Systems, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method and system for improvement of dose correction for particle b...
- Patent number 7,824,828
- Issue date Nov 2, 2010
- Cadence Design Systems, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Grant
System and method of electron beam writing
- Patent number 7,777,204
- Issue date Aug 17, 2010
- Cadence Design Systems, Inc.
- Dmitri Lapanik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stencil design and method for cell projection particle beam lithogr...
- Patent number 7,772,575
- Issue date Aug 10, 2010
- D2S, Inc.
- Kenji Yoshida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for manufacturing a reticle using character proje...
- Patent number 7,759,026
- Issue date Jul 20, 2010
- D2S, Inc.
- Akira Fujimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for design of a reticle to be manufactured using...
- Patent number 7,759,027
- Issue date Jul 20, 2010
- D2S, Inc.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for stencil design for particle beam writing
- Patent number 7,747,977
- Issue date Jun 29, 2010
- D2S, Inc.
- Dmitri Lapanik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for manufacturing a reticle using character proje...
- Patent number 7,745,078
- Issue date Jun 29, 2010
- D2S, Inc.
- Akira Fujimura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for logic design for cell projection particle bea...
- Patent number 7,579,606
- Issue date Aug 25, 2009
- D2S, Inc.
- Kenji Yoshida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout design system, layout design method and layout design progra...
- Patent number 7,013,444
- Issue date Mar 14, 2006
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,813,756
- Issue date Nov 2, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout design system, layout design method and layout design progra...
- Patent number 6,763,508
- Issue date Jul 13, 2004
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,645,842
- Issue date Nov 11, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of automatic layout design for LSI, mask set and semiconduct...
- Patent number 6,546,540
- Issue date Apr 8, 2003
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,436,804
- Issue date Aug 20, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit device, semiconductor integrated c...
- Patent number 6,262,487
- Issue date Jul 17, 2001
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Output buffer, semiconductor integrated circuit having output buffe...
- Patent number 5,994,922
- Issue date Nov 30, 1999
- Kabushiki Kaisha Toshiba
- Takahiro Aoki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power estimation method for an integrated circuit using probability...
- Patent number 5,847,966
- Issue date Dec 8, 1998
- Kabushiki Kaisha Toshiba
- Taku Uchino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for power-source wiring design of semiconducto...
- Patent number 5,404,310
- Issue date Apr 4, 1995
- Kabushiki Kaisha Toshiba
- Takashi Mitsuhashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit with dummy patterns
- Patent number 5,032,890
- Issue date Jul 16, 1991
- Kabushiki Kaisha Toshiba
- Yukihiro Ushiku
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING
- Publication number 20140011124
- Publication date Jan 9, 2014
- D2S, INC.
- Dmitri Lapanik
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING
- Publication number 20130007675
- Publication date Jan 3, 2013
- D2S, INC.
- Dmitri Lapanik
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING
- Publication number 20110265049
- Publication date Oct 27, 2011
- D2S, INC.
- Dmitri Lapanik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF ELECTRON BEAM WRITING
- Publication number 20110192994
- Publication date Aug 11, 2011
- Cadence Design Systems, Inc.
- Dmitri LANPANIK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING
- Publication number 20100229148
- Publication date Sep 9, 2010
- D2S, INC.
- Dmitri Lapanik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stencil, Stencil Design System and Method for Cell Projection Parti...
- Publication number 20100062349
- Publication date Mar 11, 2010
- D2S, INC.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD AND SYSTEM FOR MANUFACTURING A RETICLE USING CHARACTER PROJE...
- Publication number 20100055619
- Publication date Mar 4, 2010
- D2S, INC.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD FOR OPTICAL PROXIMITY CORRECTION OF A RETICLE TO BE MANUFACT...
- Publication number 20100058281
- Publication date Mar 4, 2010
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR DESIGN OF A RETICLE TO BE MANUFACTURED USING...
- Publication number 20100058282
- Publication date Mar 4, 2010
- D2S, INC.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR MANUFACTURING A RETICLE USING CHARACTER PROJE...
- Publication number 20100053579
- Publication date Mar 4, 2010
- D2S, INC.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Application
STENCIL DESIGN AND METHOD FOR IMPROVING CHARACTER DENSITY FOR CELL...
- Publication number 20090325085
- Publication date Dec 31, 2009
- D2S, INC.
- Kenji Yoshida
- B82 - NANO-TECHNOLOGY
Information Patent Application
METHOD AND SYSTEM FOR IMPROVEMENT OF DOSE CORRECTION FOR PARTICLE B...
- Publication number 20080203324
- Publication date Aug 28, 2008
- Cadence Design Systems, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method and system for logic design for cell projection particle bea...
- Publication number 20080128637
- Publication date Jun 5, 2008
- Cadence Design Systems, Inc.
- Kenji Yoshida
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method and system for lithography simulation and measurement of cri...
- Publication number 20080120073
- Publication date May 22, 2008
- Cadence Design Systems, Inc.
- Daisuke Hara
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Stencil design and method for cell projection particle beam lithogr...
- Publication number 20080116397
- Publication date May 22, 2008
- Cadence Design Systems, Inc.
- Kenji Yoshida
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method and system for improving particle beam lithography
- Publication number 20080116399
- Publication date May 22, 2008
- Cadence Design Systems, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method and system for proximity effect and dose correction for a pa...
- Publication number 20080116398
- Publication date May 22, 2008
- Cadence Design Systems, Inc.
- Daisuke Hara
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method and System for Lithography Simulation and Measurement of Cri...
- Publication number 20080118852
- Publication date May 22, 2008
- Cadence Design Systems, Inc.
- Takashi Mitsuhashi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
System and method pf electron beam writing
- Publication number 20070125967
- Publication date Jun 7, 2007
- Cadence Design Systems, Inc.
- Dmitri Lapanik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout design system, layout design method and layout design progra...
- Publication number 20040199892
- Publication date Oct 7, 2004
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automatic layout design for LSI, mask set and semiconduct...
- Publication number 20030079194
- Publication date Apr 24, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout design system, layout design method and layout design progra...
- Publication number 20030005399
- Publication date Jan 2, 2003
- Mutsunori Igarashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20020182844
- Publication date Dec 5, 2002
- Kabushiki Kaisha Toshiba
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor integrated circuit device, semiconductor integrated c...
- Publication number 20010011776
- Publication date Aug 9, 2001
- Mutsunori Igarashi
- H01 - BASIC ELECTRIC ELEMENTS

Takashi Mitsuhashi

Person

Patents Grantslast 30 patents

Method and system for stencil design for particle beam writing

System and method of electron beam writing

Cell projection charged particle beam lithography

Method and system for lithography simulation and measurement of cri...

Method and system for lithography simulation and measurement of cri...

Stencil, stencil design system and method for cell projection parti...

Method and system for proximity effect and dose correction for a pa...

Method for optical proximity correction of a reticle to be manufact...

Method and system for improving particle beam lithography

Method and system for improvement of dose correction for particle b...

System and method of electron beam writing

Stencil design and method for cell projection particle beam lithogr...

Method and system for manufacturing a reticle using character proje...

Method and system for design of a reticle to be manufactured using...

Method and system for stencil design for particle beam writing

Method and system for manufacturing a reticle using character proje...

Method and system for logic design for cell projection particle bea...

Layout design system, layout design method and layout design progra...

Method of automatic layout design for LSI, mask set and semiconduct...

Layout design system, layout design method and layout design progra...

Semiconductor integrated circuit device, semiconductor integrated c...

Method of automatic layout design for LSI, mask set and semiconduct...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit device, semiconductor integrated c...

Output buffer, semiconductor integrated circuit having output buffe...

Power estimation method for an integrated circuit using probability...

Method and apparatus for power-source wiring design of semiconducto...

Semiconductor integrated circuit with dummy patterns

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING

METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING

METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING

SYSTEM AND METHOD OF ELECTRON BEAM WRITING

METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING

Stencil, Stencil Design System and Method for Cell Projection Parti...

METHOD AND SYSTEM FOR MANUFACTURING A RETICLE USING CHARACTER PROJE...

METHOD FOR OPTICAL PROXIMITY CORRECTION OF A RETICLE TO BE MANUFACT...

METHOD AND SYSTEM FOR DESIGN OF A RETICLE TO BE MANUFACTURED USING...

METHOD AND SYSTEM FOR MANUFACTURING A RETICLE USING CHARACTER PROJE...

STENCIL DESIGN AND METHOD FOR IMPROVING CHARACTER DENSITY FOR CELL...

METHOD AND SYSTEM FOR IMPROVEMENT OF DOSE CORRECTION FOR PARTICLE B...

Method and system for logic design for cell projection particle bea...

Method and system for lithography simulation and measurement of cri...

Stencil design and method for cell projection particle beam lithogr...

Method and system for improving particle beam lithography

Method and system for proximity effect and dose correction for a pa...

Method and System for Lithography Simulation and Measurement of Cri...

System and method pf electron beam writing

Layout design system, layout design method and layout design progra...

Method of automatic layout design for LSI, mask set and semiconduct...

Layout design system, layout design method and layout design progra...

Semiconductor integrated circuit device, semiconductor integrated c...

Semiconductor integrated circuit device, semiconductor integrated c...