Takeshi Nojima

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Nara-shi, JP

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Patents Grantslast 30 patents

Information Patent Grant
Bias voltage applying circuit and semiconductor memory device
- Patent number 7,088,626
- Issue date Aug 8, 2006
- Sharp Kabushiki Kaisha
- Yasumichi Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading circuit, reference circuit, and semiconductor memory device
- Patent number 6,930,922
- Issue date Aug 16, 2005
- Sharp Kabushiki Kaisha
- Yasumichi Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory using select transistors coupled to sub-bitlin...
- Patent number 5,852,570
- Issue date Dec 22, 1998
- Sharp Kabushiki Kaisha
- Yasuhiro Hotta
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Bias voltage applying circuit and semiconductor memory device
- Publication number 20050174859
- Publication date Aug 11, 2005
- SHARP KABUSHIKI KAISHA
- Yasumichi Mori
- G11 - INFORMATION STORAGE
Information Patent Application
Reading circuit, reference circuit, and semiconductor memory device
- Publication number 20040047207
- Publication date Mar 11, 2004
- Yasumichi Mori
- G11 - INFORMATION STORAGE