Talal Kamel Jaber

Person

Autin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scan architecture and design methodology yielding significant reduc...
- Patent number 8,321,730
- Issue date Nov 27, 2012
- Intel Corporation
- Talal K. Jaber
- G01 - MEASURING TESTING
Information Patent Grant
Common test logic for multiple operation modes
- Patent number 7,734,972
- Issue date Jun 8, 2010
- Intel Corporation
- Talal Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test scan cells
- Patent number 7,437,634
- Issue date Oct 14, 2008
- Intel Corporation
- Talal K. Jaber
- G01 - MEASURING TESTING
Information Patent Grant
Flexible scan architecture
- Patent number 7,216,274
- Issue date May 8, 2007
- Intel Corporation
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor on-chip testing architecture and implementation
- Patent number 7,028,239
- Issue date Apr 11, 2006
- Intel Corporation
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan cell systems and methods
- Patent number 6,815,977
- Issue date Nov 9, 2004
- Intel Corporation
- Anil K. Sabbavarapu
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for testing high speed components using low sp...
- Patent number 6,055,658
- Issue date Apr 25, 2000
- International Business Machines Corporation
- Talal Kamel Jaber
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and methods for testing a microprocessor chip using dedic...
- Patent number 6,028,983
- Issue date Feb 22, 2000
- International Business Machines Corporation
- Talal Kamel Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance registers for pulsed logic
- Patent number 5,926,487
- Issue date Jul 20, 1999
- International Business Machines Corporation
- Terry Ivan Chappell
- G01 - MEASURING TESTING
Information Patent Grant
Methodology to test pulsed logic circuits in pseudo-static mode
- Patent number 5,748,012
- Issue date May 5, 1998
- International Business Machines Corporation
- Michael Patrick Beakes
- G01 - MEASURING TESTING
Information Patent Grant
Reduced power apparatus and method for testing high speed components
- Patent number 5,614,838
- Issue date Mar 25, 1997
- International Business Machines Corporation
- Talal K. Jaber
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUC...
- Publication number 20110161759
- Publication date Jun 30, 2011
- Talal K. Jaber
- G01 - MEASURING TESTING
Information Patent Application
Common test logic for multiple operation modes
- Publication number 20090187799
- Publication date Jul 23, 2009
- Talal Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible scan architecture
- Publication number 20070168767
- Publication date Jul 19, 2007
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible scan architecture
- Publication number 20040267504
- Publication date Dec 30, 2004
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test scan cells
- Publication number 20040243896
- Publication date Dec 2, 2004
- Intel Corporation
- Talal K. Jaber
- G01 - MEASURING TESTING
Information Patent Application
Scan cell systems and methods
- Publication number 20040119501
- Publication date Jun 24, 2004
- Anil K. Sabbavarapu
- G01 - MEASURING TESTING
Information Patent Application
Microprocessor on-chip testing architecture and implementation
- Publication number 20020087931
- Publication date Jul 4, 2002
- Talal K. Jaber
- G01 - MEASURING TESTING

Talal Kamel Jaber

Person

Patents Grantslast 30 patents

Scan architecture and design methodology yielding significant reduc...

Common test logic for multiple operation modes

Test scan cells

Flexible scan architecture

Microprocessor on-chip testing architecture and implementation

Scan cell systems and methods

Apparatus and method for testing high speed components using low sp...

Apparatus and methods for testing a microprocessor chip using dedic...

High performance registers for pulsed logic

Methodology to test pulsed logic circuits in pseudo-static mode

Reduced power apparatus and method for testing high speed components

Patents Applicationslast 30 patents

SCAN ARCHITECTURE AND DESIGN METHODOLOGY YIELDING SIGNIFICANT REDUC...

Common test logic for multiple operation modes

Flexible scan architecture

Flexible scan architecture

Test scan cells

Scan cell systems and methods

Microprocessor on-chip testing architecture and implementation