Tapan K. Nayak

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Neural network weight distribution from a grid of memory elements
- Patent number 11,521,085
- Issue date Dec 6, 2022
- International Business Machines Corporation
- Jun Sawada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized partitioning of multi-layer networks in core-based neuros...
- Patent number 11,315,020
- Issue date Apr 26, 2022
- International Business Machines Corporation
- Tapan K. Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-mode low-precision inner-product computation circuits for mas...
- Patent number 11,270,196
- Issue date Mar 8, 2022
- International Business Machines Corporation
- Jun Sawada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-software co-design of neurosynaptic systems
- Patent number 11,200,496
- Issue date Dec 14, 2021
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graph partitioning and placement for multi-chip neurosynaptic networks
- Patent number 11,157,795
- Issue date Oct 26, 2021
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection, tracking and recognition on networks of digital neurosyn...
- Patent number 11,120,561
- Issue date Sep 14, 2021
- International Business Machines Corporation
- Alexander Andreopoulos
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MODULAR NEURAL NETWORK COMPUTING APPARATUS WITH DISTRIBUTED NEURAL...
- Publication number 20220129769
- Publication date Apr 28, 2022
- International Business Machines Corporation
- Jun Sawada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFLICT-FREE, STALL-FREE, BROADCAST NETWORK ON CHIP
- Publication number 20220121951
- Publication date Apr 21, 2022
- International Business Machines Corporation
- Andrew Stephen Cassidy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL NETWORK WEIGHT DISTRIBUTION FROM A GRID OF MEMORY ELEMENTS
- Publication number 20210312305
- Publication date Oct 7, 2021
- International Business Machines Corporation
- Jun Sawada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-MODE LOW-PRECISION INNER-PRODUCT COMPUTATION CIRCUITS FOR MAS...
- Publication number 20210110245
- Publication date Apr 15, 2021
- International Business Machines Corporation
- Jun Sawada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION, TRACKING AND RECOGNITION ON NETWORKS OF DIGITAL NEUROSYN...
- Publication number 20200134843
- Publication date Apr 30, 2020
- International Business Machines Corporation
- Alexander Andreopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED PARTITIONING OF MULTI-LAYER NETWORKS IN CORE-BASED NEUROS...
- Publication number 20200097821
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Tapan K. Nayak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEUROMORPHIC SYSTEMS FOR COMPUTING CHARACTERISTICS OF A SET
- Publication number 20190266478
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-SOFTWARE CO-DESIGN OF NEUROSYNAPTIC SYSTEMS
- Publication number 20190122114
- Publication date Apr 25, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPH PARTITIONING AND PLACEMENT FOR MULTI-CHIP NEUROSYNAPTIC NETWORKS
- Publication number 20180260682
- Publication date Sep 13, 2018
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING

Tapan K. Nayak

Person

Patents Grantslast 30 patents

Neural network weight distribution from a grid of memory elements

Optimized partitioning of multi-layer networks in core-based neuros...

Multi-mode low-precision inner-product computation circuits for mas...

Hardware-software co-design of neurosynaptic systems

Graph partitioning and placement for multi-chip neurosynaptic networks

Detection, tracking and recognition on networks of digital neurosyn...

Patents Applicationslast 30 patents

MODULAR NEURAL NETWORK COMPUTING APPARATUS WITH DISTRIBUTED NEURAL...

CONFLICT-FREE, STALL-FREE, BROADCAST NETWORK ON CHIP

NEURAL NETWORK WEIGHT DISTRIBUTION FROM A GRID OF MEMORY ELEMENTS

MULTI-MODE LOW-PRECISION INNER-PRODUCT COMPUTATION CIRCUITS FOR MAS...

DETECTION, TRACKING AND RECOGNITION ON NETWORKS OF DIGITAL NEUROSYN...

OPTIMIZED PARTITIONING OF MULTI-LAYER NETWORKS IN CORE-BASED NEUROS...

NEUROMORPHIC SYSTEMS FOR COMPUTING CHARACTERISTICS OF A SET

HARDWARE-SOFTWARE CO-DESIGN OF NEUROSYNAPTIC SYSTEMS

GRAPH PARTITIONING AND PLACEMENT FOR MULTI-CHIP NEUROSYNAPTIC NETWORKS