Tapodyuti Mandal

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Hyderabad, IN

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Patents Grantslast 30 patents

Information Patent Grant
Testbench for sub-design verification
- Patent number 12,271,670
- Issue date Apr 8, 2025
- Xilinx, Inc.
- Rajvinder S. Klair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelizing simulation and hardware co-simulation of circuit desi...
- Patent number 11,475,199
- Issue date Oct 18, 2022
- Xilinx, Inc.
- Saikat Bandyopadhyay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional coverage of designs using transition bins and cross cove...
- Patent number 11,055,458
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Aparna Suresh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TESTBENCH FOR SUB-DESIGN VERIFICATION
- Publication number 20230252212
- Publication date Aug 10, 2023
- Xilinx, Inc.
- Rajvinder S. Klair
- G06 - COMPUTING CALCULATING COUNTING