TAT KIN TAN

Person

PENANG, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 12,112,997
- Issue date Oct 8, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 12,080,628
- Issue date Sep 3, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 11,652,026
- Issue date May 16, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clocking system and a method of clock synchronization
- Patent number 11,575,383
- Issue date Feb 7, 2023
- SKYECHIP SDN BHD
- Chee Hak Teh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stacked through-silicon vias for multi-device packages
- Patent number 11,398,415
- Issue date Jul 26, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 11,393,741
- Issue date Jul 19, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Generic physical layer providing a unified architecture for interfa...
- Patent number 11,373,694
- Issue date Jun 28, 2022
- SKYECHIP SDN BHD
- Soon Chieh Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods, systems and apparatus for functional safety implementation
- Patent number 11,340,978
- Issue date May 24, 2022
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro through-silicon via for transistor density scaling
- Patent number 10,903,142
- Issue date Jan 26, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for mitigating transistor aging to improve timing margins f...
- Patent number 10,714,163
- Issue date Jul 14, 2020
- Intel Corporation
- Tat Hin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
Generation of distinctive value based on true random input
- Patent number 10,452,357
- Issue date Oct 22, 2019
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed sense amplifier latch with low power rail-to-rail input...
- Patent number 10,333,689
- Issue date Jun 25, 2019
- Intel Corporation
- Pankaj Vinayak Dudulwar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods for determining resistive-capacitive component design targe...
- Patent number 10,223,483
- Issue date Mar 5, 2019
- Intel Corporation
- Tat Hin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual signal protocol input/output (I/O) buffer circuit
- Patent number 10,224,911
- Issue date Mar 5, 2019
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for extraction of electrical specifications fro...
- Patent number 10,198,545
- Issue date Feb 5, 2019
- Altera Corporation
- Tat Hin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High resolution and low power interpolator for delay chain
- Patent number 10,200,046
- Issue date Feb 5, 2019
- Intel Corporation
- Chee Seng Leong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with an increased signal bandwidth input/output...
- Patent number 10,110,225
- Issue date Oct 23, 2018
- Altera Corporation
- Ker Yon Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for enabling and disabling transistor legs in an output...
- Patent number 9,793,888
- Issue date Oct 17, 2017
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed sense amplifier latch with low power rail-to-rail input...
- Patent number 9,443,567
- Issue date Sep 13, 2016
- Intel Corporation
- Pankaj Vinayak Dudulwar
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction coding in flash memory devices
- Patent number 8,239,732
- Issue date Aug 7, 2012
- Spansion LLC
- Tat Hin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast path packet destination mechanism for network mobility via sec...
- Patent number 7,894,420
- Issue date Feb 22, 2011
- Intel Corporation
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network mobility security management
- Patent number 7,881,470
- Issue date Feb 1, 2011
- Intel Corporation
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Offset-compensated self-biased differential amplifier
- Patent number 6,967,532
- Issue date Nov 22, 2005
- Intel Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20240429131
- Publication date Dec 26, 2024
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems And Methods For Verification Of Data Erasure
- Publication number 20240380607
- Publication date Nov 14, 2024
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A Concept for Orchestration of Microservices
- Publication number 20240281220
- Publication date Aug 22, 2024
- Intel Corporation
- Tat TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
A Concept for Orchestration of Microservices
- Publication number 20240281257
- Publication date Aug 22, 2024
- Intel Corporation
- Tat TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND A METHOD FOR ALIGNING A PROGRAMMABLE CLOCK OR STROBE
- Publication number 20240192721
- Publication date Jun 13, 2024
- SKYECHIP SDN BHD
- TAT HIN TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concept for Orchestration of Microservices
- Publication number 20240143290
- Publication date May 2, 2024
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA CLEARING ATTESTATION
- Publication number 20240121079
- Publication date Apr 11, 2024
- Intel Corporation
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20230361003
- Publication date Nov 9, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20230253295
- Publication date Aug 10, 2023
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GENERIC PHYSICAL LAYER PROVIDING A UNIFIED ARCHITECTURE FOR INTERFA...
- Publication number 20220208240
- Publication date Jun 30, 2022
- SKYECHIP SDN BHD
- Soon Chieh LIM
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCKING SYSTEM AND A METHOD OF CLOCK SYNCHRONIZATION
- Publication number 20220200610
- Publication date Jun 23, 2022
- SKYECHIP SDN BHD
- CHEE HAK TEH
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Processing Module, Integrated Development Environment, Methods, and...
- Publication number 20220171659
- Publication date Jun 2, 2022
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20220157694
- Publication date May 19, 2022
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Processing Unit, Software module, Methods and Program Codes
- Publication number 20220129252
- Publication date Apr 28, 2022
- Intel Corporation
- Kamarul Zaman Abdul Rashid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO DERIVE AND VERIFY VIRTUAL PHYSICAL UNCLONA...
- Publication number 20220116234
- Publication date Apr 14, 2022
- Intel Corporation
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS AND APPARATUS TO EXPOSE A MICROSERVICE TO A SOFTWARE LAYER
- Publication number 20220012106
- Publication date Jan 13, 2022
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20210320051
- Publication date Oct 14, 2021
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED THROUGH-SILICON VIAS FOR MULTI-DEVICE PACKAGES
- Publication number 20200091040
- Publication date Mar 19, 2020
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING
- Publication number 20200043831
- Publication date Feb 6, 2020
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MITIGATING TRANSISTOR AGING TO IMPROVE TIMING MARGINS F...
- Publication number 20190267062
- Publication date Aug 29, 2019
- Intel Corporation
- Tat Hin Tan
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS, SYSTEMS AND APPARATUS FOR FUNCTIONAL SAFETY IMPLEMENTATION
- Publication number 20190250969
- Publication date Aug 15, 2019
- Intel Corporation
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques For Enabling And Disabling Transistor Legs In An Output...
- Publication number 20170264283
- Publication date Sep 14, 2017
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GENERATION OF DISTINCTIVE VALUE BASED ON TRUE RANDOM INPUT
- Publication number 20170177302
- Publication date Jun 22, 2017
- Tat Kin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT...
- Publication number 20160380753
- Publication date Dec 29, 2016
- Intel Corporation
- Pankaj Vinayak Dudulwar
- G11 - INFORMATION STORAGE
Information Patent Application
FAST PATH PACKET DESTINATION MECHANISM FOR NETWORK MOBILITY VIA SEC...
- Publication number 20110141976
- Publication date Jun 16, 2011
- Intel Corporation
- TAT KIN TAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ERROR CORRECTION CODING IN FLASH MEMORY DEVICES
- Publication number 20090113272
- Publication date Apr 30, 2009
- SPANSION LLC
- Tat Hin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST PATH PACKET DESTINATION MECHANISM FOR NETWORK MOBILITY VIA SEC...
- Publication number 20090016362
- Publication date Jan 15, 2009
- Intel Corporation
- TAT KIN TAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network mobility node authentication
- Publication number 20070234036
- Publication date Oct 4, 2007
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network mobility security management
- Publication number 20070211900
- Publication date Sep 13, 2007
- Tat Kin Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Offset-compensated self-biased differential amplifier
- Publication number 20050140442
- Publication date Jun 30, 2005
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

TAT KIN TAN

Person

Patents Grantslast 30 patents

Micro through-silicon via for transistor density scaling

Micro through-silicon via for transistor density scaling

Micro through-silicon via for transistor density scaling

Clocking system and a method of clock synchronization

Stacked through-silicon vias for multi-device packages

Micro through-silicon via for transistor density scaling

Generic physical layer providing a unified architecture for interfa...

Methods, systems and apparatus for functional safety implementation

Micro through-silicon via for transistor density scaling

Methods for mitigating transistor aging to improve timing margins f...

Generation of distinctive value based on true random input

High speed sense amplifier latch with low power rail-to-rail input...

Methods for determining resistive-capacitive component design targe...

Dual signal protocol input/output (I/O) buffer circuit

Systems and methods for extraction of electrical specifications fro...

High resolution and low power interpolator for delay chain

Integrated circuit with an increased signal bandwidth input/output...

Techniques for enabling and disabling transistor legs in an output...

High speed sense amplifier latch with low power rail-to-rail input...

Error correction coding in flash memory devices

Fast path packet destination mechanism for network mobility via sec...

Network mobility security management

Offset-compensated self-biased differential amplifier

Patents Applicationslast 30 patents

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

Systems And Methods For Verification Of Data Erasure

A Concept for Orchestration of Microservices

A Concept for Orchestration of Microservices

SYSTEM AND A METHOD FOR ALIGNING A PROGRAMMABLE CLOCK OR STROBE

Concept for Orchestration of Microservices

DATA CLEARING ATTESTATION

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

GENERIC PHYSICAL LAYER PROVIDING A UNIFIED ARCHITECTURE FOR INTERFA...

CLOCKING SYSTEM AND A METHOD OF CLOCK SYNCHRONIZATION

Processing Module, Integrated Development Environment, Methods, and...

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

Processing Unit, Software module, Methods and Program Codes

METHODS AND APPARATUS TO DERIVE AND VERIFY VIRTUAL PHYSICAL UNCLONA...

METHODS AND APPARATUS TO EXPOSE A MICROSERVICE TO A SOFTWARE LAYER

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

STACKED THROUGH-SILICON VIAS FOR MULTI-DEVICE PACKAGES

MICRO THROUGH-SILICON VIA FOR TRANSISTOR DENSITY SCALING

METHODS FOR MITIGATING TRANSISTOR AGING TO IMPROVE TIMING MARGINS F...

METHODS, SYSTEMS AND APPARATUS FOR FUNCTIONAL SAFETY IMPLEMENTATION

Techniques For Enabling And Disabling Transistor Legs In An Output...

GENERATION OF DISTINCTIVE VALUE BASED ON TRUE RANDOM INPUT

HIGH SPEED SENSE AMPLIFIER LATCH WITH LOW POWER RAIL-TO-RAIL INPUT...

FAST PATH PACKET DESTINATION MECHANISM FOR NETWORK MOBILITY VIA SEC...

ERROR CORRECTION CODING IN FLASH MEMORY DEVICES

FAST PATH PACKET DESTINATION MECHANISM FOR NETWORK MOBILITY VIA SEC...

Network mobility node authentication

Network mobility security management

Offset-compensated self-biased differential amplifier