Tazrien KAMAL

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 9,318,373
- Issue date Apr 19, 2016
- Cypress Semiconductor Corporation
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory manufacturing process with bitline isolation
- Patent number 8,673,716
- Issue date Mar 18, 2014
- Spansion LLC
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for protection against process-induced charging
- Patent number 8,445,966
- Issue date May 21, 2013
- Spansion LLC
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming bit lines for semiconductor devices
- Patent number 7,972,948
- Issue date Jul 5, 2011
- Spansion LLC
- Weidong Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming bit lines for semiconductor devices
- Patent number 7,811,915
- Issue date Oct 12, 2010
- Spansion LLC
- Weidong Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory with data retention liner
- Patent number 7,297,592
- Issue date Nov 20, 2007
- Spansion LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDC implant for mirrorbit to improve Vt roll-off and form sharper j...
- Patent number 7,176,113
- Issue date Feb 13, 2007
- Spansion LLC
- Nga-Ching Alan Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of formation of gate stack spacer and charge storage materia...
- Patent number 7,163,860
- Issue date Jan 16, 2007
- Spansion LLC
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PECVD silicon-rich oxide layer for reduced UV charging
- Patent number 7,060,554
- Issue date Jun 13, 2006
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory wordline spacer
- Patent number 7,053,446
- Issue date May 30, 2006
- Advanced Micro Devices, Inc.
- Kashmir S. Sahota
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for increasing oxygen content at bottom oxi...
- Patent number 7,033,957
- Issue date Apr 25, 2006
- FASL, LLC
- Hidehiko Shiraiwa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Undoped oxide liner/BPSG for improved data retention
- Patent number 7,023,046
- Issue date Apr 4, 2006
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Patent number 7,018,896
- Issue date Mar 28, 2006
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Disposable hard mask for memory bitline scaling
- Patent number 7,018,868
- Issue date Mar 28, 2006
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having a P+ gate and thin bottom oxide and method of...
- Patent number 6,995,423
- Issue date Feb 7, 2006
- Advanced Micro Devices, Inc.
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for reducing oxygen vacancy content in bott...
- Patent number 6,969,886
- Issue date Nov 29, 2005
- Fasl, LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hard mask spacer for sublithographic bitline
- Patent number 6,962,849
- Issue date Nov 8, 2005
- Advanced Micro Devices, Inc.
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory device and method of fabrication thereof including a b...
- Patent number 6,958,511
- Issue date Oct 25, 2005
- Fasl, LLC
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabrication of nitride layer with reduced hydrogen cont...
- Patent number 6,955,965
- Issue date Oct 18, 2005
- Fasl, LLC
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for fabrication of spacer layer with reduced hydrogen conte...
- Patent number 6,949,481
- Issue date Sep 27, 2005
- Fasl, LLC
- Arvind Halliyal
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline hard mask spacer flow for memory cell scaling
- Patent number 6,927,145
- Issue date Aug 9, 2005
- Advanced Micro Devices, Inc.
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having high work function gate and method of erasing...
- Patent number 6,912,163
- Issue date Jun 28, 2005
- Fasl, LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor memory with deuterated mate...
- Patent number 6,884,681
- Issue date Apr 26, 2005
- FASL LLC
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having A P+ gate and thin bottom oxide and method of...
- Patent number 6,885,590
- Issue date Apr 26, 2005
- Advanced Micro Devices, Inc.
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Narrow bitline using Safier for mirrorbit
- Patent number 6,872,609
- Issue date Mar 29, 2005
- Advanced Micro Devices, Inc.
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a planar structure charge trapping memory cel...
- Patent number 6,855,608
- Issue date Feb 15, 2005
- Advanced Micro Devices, Inc.
- Mark Ramsbey
- G11 - INFORMATION STORAGE
Information Patent Grant
Liner for semiconductor memories and manufacturing method therefor
- Patent number 6,803,265
- Issue date Oct 12, 2004
- FASL LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ONO fabrication process for reducing oxygen vacancy content in bott...
- Patent number 6,803,275
- Issue date Oct 12, 2004
- Fasl, LLC
- Jaeyong Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge-trapping memory arrays resistant to damage from contact hole...
- Patent number 6,794,764
- Issue date Sep 21, 2004
- Advanced Micro Devices, Inc.
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Patent number 6,774,432
- Issue date Aug 10, 2004
- Advanced Micro Devices, Inc.
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20130237022
- Publication date Sep 12, 2013
- SPANSION LLC
- David M Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES
- Publication number 20100330762
- Publication date Dec 30, 2010
- SPANSION LLC
- Weidong QIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIT LINES FOR SEMICONDUCTOR DEVICES
- Publication number 20080157187
- Publication date Jul 3, 2008
- SPANSION LLC
- Weidong QIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING
- Publication number 20080151590
- Publication date Jun 26, 2008
- David M. Rogers
- G11 - INFORMATION STORAGE
Information Patent Application
Undoped oxide liner/BPSG for improved data retention
- Publication number 20050006693
- Publication date Jan 13, 2005
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PECVD silicon-rich oxide layer for reduced UV charging
- Publication number 20050006712
- Publication date Jan 13, 2005
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device having a P+ gate and thin bottom oxide and method of...
- Publication number 20040232470
- Publication date Nov 25, 2004
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...
- Publication number 20040191989
- Publication date Sep 30, 2004
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE...
- Publication number 20040173918
- Publication date Sep 9, 2004
- Tazrien Kamal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BI...
- Publication number 20040151025
- Publication date Aug 5, 2004
- Minh V. Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device having high work function gate and method of erasing...
- Publication number 20040136240
- Publication date Jul 15, 2004
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
- Publication number 20040014290
- Publication date Jan 22, 2004
- Jean Y. Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory manufacturing process with bitline isolation
- Publication number 20030190786
- Publication date Oct 9, 2003
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS

Tazrien KAMAL

Person

Patents Grantslast 30 patents

Method and apparatus for protection against process-induced charging

Memory manufacturing process with bitline isolation

Method and apparatus for protection against process-induced charging

Method for forming bit lines for semiconductor devices

Method for forming bit lines for semiconductor devices

Semiconductor memory with data retention liner

LDC implant for mirrorbit to improve Vt roll-off and form sharper j...

Method of formation of gate stack spacer and charge storage materia...

PECVD silicon-rich oxide layer for reduced UV charging

Memory wordline spacer

ONO fabrication process for increasing oxygen content at bottom oxi...

Undoped oxide liner/BPSG for improved data retention

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

Disposable hard mask for memory bitline scaling

Memory device having a P+ gate and thin bottom oxide and method of...

ONO fabrication process for reducing oxygen vacancy content in bott...

Hard mask spacer for sublithographic bitline

Flash memory device and method of fabrication thereof including a b...

Process for fabrication of nitride layer with reduced hydrogen cont...

Process for fabrication of spacer layer with reduced hydrogen conte...

Bitline hard mask spacer flow for memory cell scaling

Memory device having high work function gate and method of erasing...

Method of manufacturing a semiconductor memory with deuterated mate...

Memory device having A P+ gate and thin bottom oxide and method of...

Narrow bitline using Safier for mirrorbit

Method of fabricating a planar structure charge trapping memory cel...

Liner for semiconductor memories and manufacturing method therefor

ONO fabrication process for reducing oxygen vacancy content in bott...

Charge-trapping memory arrays resistant to damage from contact hole...

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES

BIT LINES FOR SEMICONDUCTOR DEVICES

METHOD AND APPARATUS FOR PROTECTION AGAINST PROCESS-INDUCED CHARGING

Undoped oxide liner/BPSG for improved data retention

PECVD silicon-rich oxide layer for reduced UV charging

Memory device having a P+ gate and thin bottom oxide and method of...

UV-blocking layer for reducing UV-induced charging of SONOS dual-bi...

CHARGE-TRAPPING MEMORY ARRAYS RESISTANT TO DAMAGE FROM CONTACT HOLE...

UV-BLOCKING LAYER FOR REDUCING UV-INDUCED CHARGING OF SONOS DUAL-BI...

Memory device having high work function gate and method of erasing...

HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS

Memory manufacturing process with bitline isolation