Techi WONG

Person

Zhubei City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with improved interposer structure
- Patent number 12,308,313
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided routing in 3D semiconductor system-in-package structure...
- Patent number 12,308,322
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out package with controllable standoff
- Patent number 12,300,592
- Issue date May 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with improved interposer structure
- Patent number 12,237,262
- Issue date Feb 25, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out package with cavity substrate
- Patent number 12,199,084
- Issue date Jan 14, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of manufacturing
- Patent number 12,176,337
- Issue date Dec 24, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages and methods of forming same
- Patent number 12,170,274
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous fan-out structure and method of manufacture
- Patent number 12,131,984
- Issue date Oct 29, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming chip package structure
- Patent number 12,100,666
- Issue date Sep 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming package structure
- Patent number 12,094,819
- Issue date Sep 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packages with ring-shaped substrates
- Patent number 12,074,104
- Issue date Aug 27, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package with redistribution structure having multiple chips
- Patent number 12,046,548
- Issue date Jul 23, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation method of chip package with fan-out feature
- Patent number 11,948,892
- Issue date Apr 2, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out package with cavity substrate
- Patent number 11,855,059
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out package with controllable standoff
- Patent number 11,854,955
- Issue date Dec 26, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with improved interposer structure
- Patent number 11,848,265
- Issue date Dec 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided routing in 3D SiP structure
- Patent number 11,824,007
- Issue date Nov 21, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with fan-out structures
- Patent number 11,764,159
- Issue date Sep 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package structure with molding layer and method for forming th...
- Patent number 11,682,599
- Issue date Jun 20, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package with redistribution structure having multiple chips
- Patent number 11,670,577
- Issue date Jun 6, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous fan-out structure and method of manufacture
- Patent number 11,646,256
- Issue date May 9, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and formation method of chip package with conductive supp...
- Patent number 11,600,573
- Issue date Mar 7, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming chip package structure
- Patent number 11,600,575
- Issue date Mar 7, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package and method
- Patent number 11,527,474
- Issue date Dec 13, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of manufacturing
- Patent number 11,430,776
- Issue date Aug 30, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out package with cavity substrate
- Patent number 11,380,666
- Issue date Jul 5, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and formation method of chip package with fan-out feature
- Patent number 11,362,010
- Issue date Jun 14, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Meng-Liang Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-sided routing in 3D SiP structure
- Patent number 11,322,447
- Issue date May 3, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with fan-out structures
- Patent number 11,322,449
- Issue date May 3, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor packages and methods of forming same
- Patent number 11,296,065
- Issue date Apr 5, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor Devices and Methods of Manufacturing
- Publication number 20250079428
- Publication date Mar 6, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heterogeneous Fan-Out Structure and Method of Manufacture
- Publication number 20250038087
- Publication date Jan 30, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
- Publication number 20240379646
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20240379577
- Publication date Nov 14, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE
- Publication number 20240363533
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE HAVING MULTIPLE CHIPS
- Publication number 20240347439
- Publication date Oct 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE WITH FAN-OUT FEATURE AND METHOD FOR FORMING THE SAME
- Publication number 20240203893
- Publication date Jun 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Package with Cavity Substrate
- Publication number 20240105705
- Publication date Mar 28, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE
- Publication number 20240071909
- Publication date Feb 29, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-SIDED ROUTING IN 3D SIP STRUCTURE
- Publication number 20230387028
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE
- Publication number 20230378055
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH FAN-OUT STRUCTURES
- Publication number 20230378078
- Publication date Nov 23, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Package with Controllable Standoff
- Publication number 20230361015
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGE WITH REDISTRIBUTION STRUCTURE HAVING MULTIPLE CHIPS
- Publication number 20230260890
- Publication date Aug 17, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Heterogeneous Fan-Out Structure and Method of Manufacture
- Publication number 20230253301
- Publication date Aug 10, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING CHIP PACKAGE STRUCTURE
- Publication number 20230207477
- Publication date Jun 29, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Packages
- Publication number 20230105359
- Publication date Apr 6, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Devices and Methods of Manufacturing
- Publication number 20220359489
- Publication date Nov 10, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Package with Cavity Substrate
- Publication number 20220344317
- Publication date Oct 27, 2022
- Taiwan Semiconductor Manufacturing CO.,LTD.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE STRUCTURE WITH FAN-OUT FEATURE
- Publication number 20220310468
- Publication date Sep 29, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Meng-Liang Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
- Publication number 20220216192
- Publication date Jul 7, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-sided Routing in 3D SiP Structure
- Publication number 20220199541
- Publication date Jun 23, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE
- Publication number 20220108956
- Publication date Apr 7, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
- Publication number 20210391314
- Publication date Dec 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Shin-Puu Jeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING
- Publication number 20210391317
- Publication date Dec 16, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING PACKAGE STRUCTURE
- Publication number 20210384125
- Publication date Dec 9, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Hao Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE
- Publication number 20210375755
- Publication date Dec 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Wen Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Package with Controllable Standoff
- Publication number 20210351118
- Publication date Nov 11, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Po-Hao TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING CHIP PACKAGE STRUCTURE
- Publication number 20210343652
- Publication date Nov 4, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH FAN-OUT STRUCTURES
- Publication number 20210320069
- Publication date Oct 14, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shin-Puu JENG
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Semiconductor package with improved interposer structure

Dual-sided routing in 3D semiconductor system-in-package structure...

Fan-out package with controllable standoff

Semiconductor package with improved interposer structure

Fan-out package with cavity substrate

Semiconductor devices and methods of manufacturing

Semiconductor packages and methods of forming same

Heterogeneous fan-out structure and method of manufacture

Method for forming chip package structure

Method for forming package structure

Integrated circuit packages with ring-shaped substrates

Chip package with redistribution structure having multiple chips

Formation method of chip package with fan-out feature

Fan-out package with cavity substrate

Fan-out package with controllable standoff

Semiconductor package with improved interposer structure

Dual-sided routing in 3D SiP structure

Package with fan-out structures

Chip package structure with molding layer and method for forming th...

Chip package with redistribution structure having multiple chips

Heterogeneous fan-out structure and method of manufacture

Structure and formation method of chip package with conductive supp...

Method for forming chip package structure

Integrated circuit package and method

Semiconductor devices and methods of manufacturing

Fan-out package with cavity substrate

Structure and formation method of chip package with fan-out feature

Dual-sided routing in 3D SiP structure

Package with fan-out structures

Semiconductor packages and methods of forming same

Patents Applicationslast 30 patents

Semiconductor Devices and Methods of Manufacturing

Heterogeneous Fan-Out Structure and Method of Manufacture

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

PACKAGE STRUCTURE

CHIP PACKAGE HAVING MULTIPLE CHIPS

CHIP PACKAGE WITH FAN-OUT FEATURE AND METHOD FOR FORMING THE SAME

Fan-Out Package with Cavity Substrate

SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE

DUAL-SIDED ROUTING IN 3D SIP STRUCTURE

SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE

PACKAGE WITH FAN-OUT STRUCTURES

Fan-Out Package with Controllable Standoff

CHIP PACKAGE WITH REDISTRIBUTION STRUCTURE HAVING MULTIPLE CHIPS

Heterogeneous Fan-Out Structure and Method of Manufacture

METHOD FOR FORMING CHIP PACKAGE STRUCTURE

Integrated Circuit Packages

Semiconductor Devices and Methods of Manufacturing

Fan-Out Package with Cavity Substrate

PACKAGE STRUCTURE WITH FAN-OUT FEATURE

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

Dual-sided Routing in 3D SiP Structure

FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING

METHOD FOR FORMING PACKAGE STRUCTURE

SEMICONDUCTOR PACKAGE WITH IMPROVED INTERPOSER STRUCTURE

Fan-Out Package with Controllable Standoff

METHOD FOR FORMING CHIP PACKAGE STRUCTURE

PACKAGE WITH FAN-OUT STRUCTURES