Teck Jung Tang

Person

Ballston Lake, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits including organic interlayer dielectric layers...
- Patent number 9,576,894
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES, INC.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of fabricating BEOL interlayer structures
- Patent number 9,362,162
- Issue date Jun 7, 2016
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced capacitance interlayer structures and fabrication methods
- Patent number 9,142,451
- Issue date Sep 22, 2015
- GLOBALFOUNDRIES Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a FinFET semiconductor device with undoped fins
- Patent number 9,105,507
- Issue date Aug 11, 2015
- GLOBALFOUNDRIES Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a finfet semiconductor device with undoped fins
- Patent number 8,969,932
- Issue date Mar 3, 2015
- GLOBALFOUNDRIES Inc.
- Andy C. Wei
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
3D integrated circuit system with connecting via structure and meth...
- Patent number 8,637,993
- Issue date Jan 28, 2014
- GLOBALFOUNDRIES, INC.
- Chun Yu Wong
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS...
- Publication number 20160358851
- Publication date Dec 8, 2016
- GLOBALFOUNDRIES, Inc.
- Sunil Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES
- Publication number 20160049327
- Publication date Feb 18, 2016
- GLOBALFOUNDRIES INC.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS
- Publication number 20150348907
- Publication date Dec 3, 2015
- GLOBAL FOUNDRIES Inc.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS
- Publication number 20150123214
- Publication date May 7, 2015
- GLOBALFOUNDRIES INC.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS
- Publication number 20150076705
- Publication date Mar 19, 2015
- GLOBALFOUNDRIES Inc.
- Sunil Kumar SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS
- Publication number 20140159126
- Publication date Jun 12, 2014
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METH...
- Publication number 20130277854
- Publication date Oct 24, 2013
- GLOBALFOUNDRIES INC.
- Chun Yu Wong
- H01 - BASIC ELECTRIC ELEMENTS

Teck Jung Tang

Person

Patents Grantslast 30 patents

Integrated circuits including organic interlayer dielectric layers...

Methods of fabricating BEOL interlayer structures

Reduced capacitance interlayer structures and fabrication methods

Methods of forming a FinFET semiconductor device with undoped fins

Methods of forming a finfet semiconductor device with undoped fins

3D integrated circuit system with connecting via structure and meth...

Patents Applicationslast 30 patents

INTEGRATED CIRCUITS INCLUDING ORGANIC INTERLAYER DIELECTRIC LAYERS...

METHODS OF FABRICATING BEOL INTERLAYER STRUCTURES

REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS

METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS

REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS

METHODS OF FORMING A FINFET SEMICONDUCTOR DEVICE WITH UNDOPED FINS

3D INTEGRATED CIRCUIT SYSTEM WITH CONNECTING VIA STRUCTURE AND METH...