Teik-Chung Tan

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Prefetching in a lower level exclusive cache hierarchy
- Patent number 10,963,388
- Issue date Mar 30, 2021
- Samsung Electronics Co., Ltd.
- Vikas Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid tag scheduler to broadcast scheduler entry tags for picked i...
- Patent number 9,727,340
- Issue date Aug 8, 2017
- Advanced Micro Devices, Inc.
- Michael Achenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Micro-ops including packed source and destination fields
- Patent number 9,395,988
- Issue date Jul 19, 2016
- Samsung Electronics Co., Ltd.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Way preparation for accessing a cache
- Patent number 9,256,544
- Issue date Feb 9, 2016
- Advanced Micro Devices, Inc.
- Matthew M. Crum
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fast flag generation
- Patent number 7,783,692
- Issue date Aug 24, 2010
- Advanced Micro Devices, Inc.
- Wing-Shek Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple control sequences per row of microcode ROM
- Patent number 7,610,476
- Issue date Oct 27, 2009
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast hardware divider
- Patent number 7,584,237
- Issue date Sep 1, 2009
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a shuffle unit to implement shift operations in a processor
- Patent number 7,464,255
- Issue date Dec 9, 2008
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Organization of dirty bits for a write-back cache
- Patent number 7,380,070
- Issue date May 27, 2008
- Texas Instruments Incorporated
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor including bank-pipelined cache with asynchronous dat...
- Patent number 7,124,236
- Issue date Oct 17, 2006
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alternate phase dual compression-tree multiplier
- Patent number 7,028,068
- Issue date Apr 11, 2006
- Advanced Micro Devices, Inc.
- Kelvin D. Goveas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sectored least-recently-used cache replacement
- Patent number 6,823,427
- Issue date Nov 23, 2004
- Advanced Micro Devices, Inc.
- Benjamin T. Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to provide fixed latency early response in a s...
- Patent number 6,760,392
- Issue date Jul 6, 2004
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for speculatively invalidating lines in a cache
- Patent number 6,725,337
- Issue date Apr 20, 2004
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stride based prefetcher with confidence counter and dynamic prefetc...
- Patent number 6,571,318
- Issue date May 27, 2003
- Advanced Micro Devices, Inc.
- Benjamin T. Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to transfer data in a system with multiple clock domains usi...
- Patent number 6,424,688
- Issue date Jul 23, 2002
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implementing a least recently used cache r...
- Patent number 6,408,364
- Issue date Jun 18, 2002
- Advanced Micro Devices, Inc.
- Teik-Chang Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for modifying status bits in a reorder buffer...
- Patent number 5,920,710
- Issue date Jul 6, 1999
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reorder buffer including a circuit for selecting a designated mask...
- Patent number 5,870,579
- Issue date Feb 9, 1999
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density dynamic bus routing scheme
- Patent number 5,815,031
- Issue date Sep 29, 1998
- Advanced Micro Devices, Inc.
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PREFETCHING IN A LOWER LEVEL EXCLUSIVE CACHE HIERARCHY
- Publication number 20200401523
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Vikas SINHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID TAG SCHEDULER
- Publication number 20150026436
- Publication date Jan 22, 2015
- Advanced Micro Devices, Inc.
- Michael Achenbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICRO-OPS INCLUDING PACKED SOURCE AND DESTINATION FIELDS
- Publication number 20140258687
- Publication date Sep 11, 2014
- Teik-Chung TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAY PREPARATION FOR ACCESSING A CACHE
- Publication number 20140181407
- Publication date Jun 26, 2014
- Advanced Micro Devices, Inc.
- Matthew M. Crum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bank conflict avoidance in a multi-banked cache system
- Publication number 20060195677
- Publication date Aug 31, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Organization of dirty bits for a write-back cache
- Publication number 20060184745
- Publication date Aug 17, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Teik-Chung Tan
- G06 - COMPUTING CALCULATING COUNTING

Teik-Chung Tan

Person

Patents Grantslast 30 patents

Prefetching in a lower level exclusive cache hierarchy

Hybrid tag scheduler to broadcast scheduler entry tags for picked i...

Micro-ops including packed source and destination fields

Way preparation for accessing a cache

Fast flag generation

Multiple control sequences per row of microcode ROM

Fast hardware divider

Using a shuffle unit to implement shift operations in a processor

Organization of dirty bits for a write-back cache

Microprocessor including bank-pipelined cache with asynchronous dat...

Alternate phase dual compression-tree multiplier

Sectored least-recently-used cache replacement

Method and apparatus to provide fixed latency early response in a s...

Method and system for speculatively invalidating lines in a cache

Stride based prefetcher with confidence counter and dynamic prefetc...

Method to transfer data in a system with multiple clock domains usi...

Apparatus and method for implementing a least recently used cache r...

Apparatus and method for modifying status bits in a reorder buffer...

Reorder buffer including a circuit for selecting a designated mask...

High density dynamic bus routing scheme

Patents Applicationslast 30 patents

PREFETCHING IN A LOWER LEVEL EXCLUSIVE CACHE HIERARCHY

HYBRID TAG SCHEDULER

MICRO-OPS INCLUDING PACKED SOURCE AND DESTINATION FIELDS

WAY PREPARATION FOR ACCESSING A CACHE

Bank conflict avoidance in a multi-banked cache system

Organization of dirty bits for a write-back cache