Tejvansh Singh Soni

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Fremont, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Derived clock synchronization for reduced skew and jitter
- Patent number 7,526,666
- Issue date Apr 28, 2009
- NVIDIA Corporation
- Tejvansh S. Soni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for a high speed, bi-directional, zero turnaround...
- Patent number 6,686,774
- Issue date Feb 3, 2004
- Raza Microelectronics, Inc.
- Tejvansh Singh Soni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single phase edge trigger register
- Patent number 6,388,471
- Issue date May 14, 2002
- SandCraft, Inc.
- Wei-ping Lu
- H03 - BASIC ELECTRONIC CIRCUITRY