Tek Po Rinus Lee

Person

Malta, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device with highly active acceptor doping and method of production...
- Patent number 10,886,178
- Issue date Jan 5, 2021
- GLOBALFOUNDRIES Inc.
- Tek Po Rinus Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Spacer structures for a transistor device
- Patent number 10,872,979
- Issue date Dec 22, 2020
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming spacers adjacent gate structures of a transistor...
- Patent number 10,629,739
- Issue date Apr 21, 2020
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common metal contact regions having different Schottky barrier heig...
- Patent number 10,276,683
- Issue date Apr 30, 2019
- GLOBALFOUNDRIES Inc.
- Tek Po Rinus Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus, and manufacturing system for self-aligned patte...
- Patent number 10,263,122
- Issue date Apr 16, 2019
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a protection device having an inner contact spac...
- Patent number 10,242,982
- Issue date Mar 26, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical-transport transistors with self-aligned contacts
- Patent number 10,230,000
- Issue date Mar 12, 2019
- GLOBALFOUNDRIES Inc.
- Emilie Bourjot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit products that include FinFET devices and a prote...
- Patent number 10,170,544
- Issue date Jan 1, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried contact structures for a vertical field-effect transistor
- Patent number 10,109,714
- Issue date Oct 23, 2018
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanosheet field-effect transistor with full dielectric isolation
- Patent number 10,103,238
- Issue date Oct 16, 2018
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a protection layer on an isolation region of IC...
- Patent number 9,876,077
- Issue date Jan 23, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried contact structures for a vertical field-effect transistor
- Patent number 9,831,317
- Issue date Nov 28, 2017
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common metal contact regions having different Schottky barrier heig...
- Patent number 9,812,543
- Issue date Nov 7, 2017
- GLOBALFOUNDRIES Inc.
- Tek Po Rinus Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming symmetrical stress liners for strained CMOS vertical nanowi...
- Patent number 9,570,552
- Issue date Feb 14, 2017
- GLOBALFOUNDRIES Inc.
- Tek Po Rinus Lee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW RESISTANCE LINER
- Publication number 20250157932
- Publication date May 15, 2025
- TOKYO ELECTRON LIMITED
- Tek Po Rinus Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SEMICONDUCTOR PROCESSING
- Publication number 20250105002
- Publication date Mar 27, 2025
- TOKYO ELECTRON LIMITED
- Hunter Frost
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
NOVEL SPACER STRUCTURES FOR A TRANSISTOR DEVICE
- Publication number 20200168731
- Publication date May 28, 2020
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE WITH HIGHLY ACTIVE ACCEPTOR DOPING AND METHOD OF PRODUCTION...
- Publication number 20200066593
- Publication date Feb 27, 2020
- GLOBALFOUNDRIES INC.
- Tek Po Rinus LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SPACERS ADJACENT GATE STRUCTURES OF A TRANSISTOR...
- Publication number 20200027979
- Publication date Jan 23, 2020
- GLOBALFOUNDRIES INC.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL-TRANSPORT TRANSISTORS WITH SELF-ALIGNED CONTACTS
- Publication number 20190051757
- Publication date Feb 14, 2019
- GLOBALFOUNDRIES INC.
- Emilie Bourjot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPAC...
- Publication number 20180261595
- Publication date Sep 13, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR
- Publication number 20180254327
- Publication date Sep 6, 2018
- GLOBALFOUNDRIES Inc.
- Hui Zang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF BAND-EDGE CONTACTS
- Publication number 20180138177
- Publication date May 17, 2018
- GLOBALFOUNDRIES INC.
- Tek Po Rinus LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTE...
- Publication number 20180102409
- Publication date Apr 12, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIG...
- Publication number 20180019313
- Publication date Jan 18, 2018
- GLOBALFOUNDRIES INC.
- Tek Po Rinus LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC...
- Publication number 20180006111
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIG...
- Publication number 20170256624
- Publication date Sep 7, 2017
- GLOBALFOUNDRIES INC.
- Tek Po Rinus LEE
- H01 - BASIC ELECTRIC ELEMENTS

Tek Po Rinus Lee

Person

Patents Grantslast 30 patents

Device with highly active acceptor doping and method of production...

Spacer structures for a transistor device

Methods of forming spacers adjacent gate structures of a transistor...

Common metal contact regions having different Schottky barrier heig...

Methods, apparatus, and manufacturing system for self-aligned patte...

Method for forming a protection device having an inner contact spac...

Vertical-transport transistors with self-aligned contacts

Integrated circuit products that include FinFET devices and a prote...

Buried contact structures for a vertical field-effect transistor

Nanosheet field-effect transistor with full dielectric isolation

Methods of forming a protection layer on an isolation region of IC...

Buried contact structures for a vertical field-effect transistor

Common metal contact regions having different Schottky barrier heig...

Forming symmetrical stress liners for strained CMOS vertical nanowi...

Patents Applicationslast 30 patents

LOW RESISTANCE LINER

METHOD FOR SEMICONDUCTOR PROCESSING

NOVEL SPACER STRUCTURES FOR A TRANSISTOR DEVICE

DEVICE WITH HIGHLY ACTIVE ACCEPTOR DOPING AND METHOD OF PRODUCTION...

METHODS OF FORMING SPACERS ADJACENT GATE STRUCTURES OF A TRANSISTOR...

VERTICAL-TRANSPORT TRANSISTORS WITH SELF-ALIGNED CONTACTS

METHOD FOR FORMING A PROTECTION DEVICE HAVING AN INNER CONTACT SPAC...

BURIED CONTACT STRUCTURES FOR A VERTICAL FIELD-EFFECT TRANSISTOR

FORMATION OF BAND-EDGE CONTACTS

INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTE...

COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIG...

METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC...

COMMON METAL CONTACT REGIONS HAVING DIFFERENT SCHOTTKY BARRIER HEIG...