Terence J. Magee

Person

San Francisco, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three dimensional circuit systems and methods having memory hierarc...
- Patent number 11,789,641
- Issue date Oct 17, 2023
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recalibration of source synchronous systems
- Patent number 10,103,718
- Issue date Oct 16, 2018
- Xilinx, Inc.
- Richard W. Swanson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for intersymbol interference compensation
- Patent number 10,009,197
- Issue date Jun 26, 2018
- Xilinx, Inc.
- Terence J. Magee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed serial data interface for a physical layer interface
- Patent number 9,557,766
- Issue date Jan 31, 2017
- Xilinx, Inc.
- Terence Magee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Calibration in a control device receiving from a source synchronous...
- Patent number 9,355,696
- Issue date May 31, 2016
- Xilinx, Inc.
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Receivers and methods of enabling the calibration of circuits recei...
- Patent number 9,331,701
- Issue date May 3, 2016
- Xilinx, Inc.
- Xiaoqian Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic selection of output delay in a memory control device
- Patent number 9,330,749
- Issue date May 3, 2016
- Xilinx, Inc.
- Dhruv Choksey
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for gating a strobe signal from a memory and s...
- Patent number 9,324,409
- Issue date Apr 26, 2016
- Xilinx, Inc.
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Read clock forwarding for multiple source-synchronous memory interf...
- Patent number 9,281,049
- Issue date Mar 8, 2016
- Xilinx, Inc.
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for VT invariant SDRAM write leveling and fast...
- Patent number 9,224,444
- Issue date Dec 29, 2015
- Xilinx, Inc.
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Generic low power strobe based system and method for interfacing me...
- Patent number 8,743,634
- Issue date Jun 3, 2014
- LSI Corporation
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-linear common coarse delay system and method for delaying data...
- Patent number 8,453,096
- Issue date May 28, 2013
- LSI Corporation
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple memory standard physical layer macro function
- Patent number 7,969,799
- Issue date Jun 28, 2011
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable high-speed memory interface subsystem
- Patent number 7,865,661
- Issue date Jan 4, 2011
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
System for glitch-free delay updates of a standard cell-based progr...
- Patent number 7,605,628
- Issue date Oct 20, 2009
- LSI Corporation
- Terence J. Magee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for compensating for PVT variation effects on the...
- Patent number 7,454,303
- Issue date Nov 18, 2008
- LSI Logic Corporation
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable high-speed memory interface subsystem
- Patent number 7,437,500
- Issue date Oct 14, 2008
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Input Output Banks of a Programmable Logic Device
- Publication number 20230140547
- Publication date May 4, 2023
- Intel Corporation
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Source Synchronous Partition of an SDRAM Controller Subsystem
- Publication number 20230123826
- Publication date Apr 20, 2023
- Intel Corporation
- Terence Magee
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques For Synchronous Accesses To Storage Circuits
- Publication number 20230118912
- Publication date Apr 20, 2023
- Intel Corporation
- Jeffrey Schulz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three Dimensional Circuit Systems And Methods Having Memory Hierarc...
- Publication number 20220405005
- Publication date Dec 22, 2022
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECALIBRATION OF SOURCE SYNCHRONOUS SYSTEMS
- Publication number 20180294802
- Publication date Oct 11, 2018
- Xilinx, Inc.
- Richard W. Swanson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CALIBRATION IN A CONTROL DEVICE RECEIVING FROM A SOURCE SYNCHRONOUS...
- Publication number 20160133305
- Publication date May 12, 2016
- Xilinx, Inc.
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE
- Publication number 20160111139
- Publication date Apr 21, 2016
- Xilinx, Inc.
- Dhruv Choksey
- G11 - INFORMATION STORAGE
Information Patent Application
NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA...
- Publication number 20120194248
- Publication date Aug 2, 2012
- LSI CORPORATION
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Application
GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING ME...
- Publication number 20120195141
- Publication date Aug 2, 2012
- LSI CORPORATION
- Terence J. Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple memory standard physical layer macro function
- Publication number 20090091987
- Publication date Apr 9, 2009
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable high-speed memory interface subsystem
- Publication number 20090043955
- Publication date Feb 12, 2009
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGR...
- Publication number 20080278210
- Publication date Nov 13, 2008
- Terence J. Magee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for compensating for PVT variation effects on the...
- Publication number 20080150610
- Publication date Jun 26, 2008
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable high-speed memory interface subsystem
- Publication number 20070033337
- Publication date Feb 8, 2007
- LSI Logic Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE

Terence J. Magee

Person

Patents Grantslast 30 patents

Three dimensional circuit systems and methods having memory hierarc...

Recalibration of source synchronous systems

Method and apparatus for intersymbol interference compensation

High-speed serial data interface for a physical layer interface

Calibration in a control device receiving from a source synchronous...

Receivers and methods of enabling the calibration of circuits recei...

Dynamic selection of output delay in a memory control device

Method and apparatus for gating a strobe signal from a memory and s...

Read clock forwarding for multiple source-synchronous memory interf...

Method and apparatus for VT invariant SDRAM write leveling and fast...

Generic low power strobe based system and method for interfacing me...

Non-linear common coarse delay system and method for delaying data...

Multiple memory standard physical layer macro function

Configurable high-speed memory interface subsystem

System for glitch-free delay updates of a standard cell-based progr...

System and method for compensating for PVT variation effects on the...

Configurable high-speed memory interface subsystem

Patents Applicationslast 30 patents

Input Output Banks of a Programmable Logic Device

Source Synchronous Partition of an SDRAM Controller Subsystem

Techniques For Synchronous Accesses To Storage Circuits

Three Dimensional Circuit Systems And Methods Having Memory Hierarc...

RECALIBRATION OF SOURCE SYNCHRONOUS SYSTEMS

CALIBRATION IN A CONTROL DEVICE RECEIVING FROM A SOURCE SYNCHRONOUS...

DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE

NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA...

GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING ME...

Multiple memory standard physical layer macro function

Configurable high-speed memory interface subsystem

SYSTEM FOR GLITCH-FREE DELAY UPDATES OF A STANDARD CELL-BASED PROGR...

System and method for compensating for PVT variation effects on the...

Configurable high-speed memory interface subsystem