Terumine Hayashi

Person

Hitachi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method of determining routes for a plurality of wiring connections...
- Patent number 5,657,242
- Issue date Aug 12, 1997
- Hitachi, Ltd.
- Yutaka Sekiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic circuit with additional circuit for carrying out delay test
- Patent number 5,329,532
- Issue date Jul 12, 1994
- Hitachi, Ltd.
- Mitsuji Ikeda
- G01 - MEASURING TESTING
Information Patent Grant
Placement optimizing method/apparatus and apparatus for designing s...
- Patent number 5,200,908
- Issue date Apr 6, 1993
- Hitachi, Ltd.
- Hiroshi Date
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing element placement and method an...
- Patent number 5,144,563
- Issue date Sep 1, 1992
- Hitachi, Ltd.
- Hiroshi Date
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for deleting unused gates and method for manufacturing maste...
- Patent number 4,960,724
- Issue date Oct 2, 1990
- Hitachi, Ltd.
- Shoichi Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory incorporating logic LSI and method for testing the same LSI
- Patent number 4,956,818
- Issue date Sep 11, 1990
- Hitachi, Ltd.
- Kazumi Hatayama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for diagnosing a LSI chip
- Patent number 4,710,930
- Issue date Dec 1, 1987
- Hitachi, Ltd.
- Kazumi Hatayama
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit device
- Patent number 4,701,922
- Issue date Oct 20, 1987
- Hitachi, Ltd.
- Shigeo Kuboki
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit device and method of diagnosing the same
- Patent number 4,613,970
- Issue date Sep 23, 1986
- Hitachi, Ltd.
- Ikuro Masuda
- G01 - MEASURING TESTING

Terumine Hayashi

Person

Patents Grantslast 30 patents

Method of determining routes for a plurality of wiring connections...

Logic circuit with additional circuit for carrying out delay test

Placement optimizing method/apparatus and apparatus for designing s...

Method and apparatus for optimizing element placement and method an...

Method for deleting unused gates and method for manufacturing maste...

Memory incorporating logic LSI and method for testing the same LSI

Method and apparatus for diagnosing a LSI chip

Integrated circuit device

Integrated circuit device and method of diagnosing the same