Tetsuo Hironaka

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Hiroshima-shi, JP

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Patents Grantslast 30 patents

Information Patent Grant
Multi-port integrated cache
- Patent number 7,694,077
- Issue date Apr 6, 2010
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-port integrated cache
- Patent number 7,360,024
- Issue date Apr 15, 2008
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register access scheduling method for multi-bank register file of a...
- Patent number 7,178,008
- Issue date Feb 13, 2007
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with synchronous bank architecture
- Patent number 7,117,291
- Issue date Oct 3, 2006
- Semiconductor Technology Academic Research Center
- Hans Jurgen Mattausch
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MULTI-PORT INTEGRATED CACHE
- Publication number 20080222360
- Publication date Sep 11, 2008
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory with synchronous bank architecture
- Publication number 20050125594
- Publication date Jun 9, 2005
- Semiconductor Technology Academic Research Center
- Hans Jurgen Mattausch
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-port integrated cache
- Publication number 20040088489
- Publication date May 6, 2004
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel processor
- Publication number 20030200422
- Publication date Oct 23, 2003
- Semiconductor Technology Academic Research Center
- Tetsuo Hironaka
- G06 - COMPUTING CALCULATING COUNTING