Thai Minh Nguyen

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Closed-loop adaptive voltage scaling for integrated circuits
- Patent number 9,158,319
- Issue date Oct 13, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Grant
Testing a circuit with compressed scan chain subsets
- Patent number 7,831,876
- Issue date Nov 9, 2010
- LSI Corporation
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Grant
On-chip circuit for transition delay fault test pattern generation...
- Patent number 7,640,461
- Issue date Dec 29, 2009
- LSI Logic Corporation
- Thai-Minh Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Test clocking scheme
- Patent number 7,444,560
- Issue date Oct 28, 2008
- LSI Corporation
- Thai M. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of generating an efficient stuck-at fault and transition del...
- Patent number 7,058,909
- Issue date Jun 6, 2006
- LSI Logic Corporation
- Cam L. Lu
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing integrated circuit core modules
- Patent number 6,888,367
- Issue date May 3, 2005
- LSI Logic Corporation
- Thai M. Nguyen
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF ADVANCED TRAFFIC MANAGEMENT
- Publication number 20200357279
- Publication date Nov 12, 2020
- Jaime Rodriguez
- G08 - SIGNALLING
Information Patent Application
CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
- Publication number 20150109052
- Publication date Apr 23, 2015
- LSI Corporation
- Manjunatha Gowda
- G05 - CONTROLLING REGULATING
Information Patent Application
ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT ID...
- Publication number 20110279171
- Publication date Nov 17, 2011
- LSI Corporation
- Lihui Cao
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION...
- Publication number 20090125769
- Publication date May 14, 2009
- Thai-Minh Nguyen
- G01 - MEASURING TESTING
Information Patent Application
TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS
- Publication number 20090106613
- Publication date Apr 23, 2009
- LSI Corporation
- Saket K. Goyal
- G01 - MEASURING TESTING
Information Patent Application
Method of testing scan chain integrity and tester setup for scan bl...
- Publication number 20060136795
- Publication date Jun 22, 2006
- LSI Logic Corporation
- Arun Gunda
- G01 - MEASURING TESTING
Information Patent Application
Test clocking scheme
- Publication number 20060095816
- Publication date May 4, 2006
- Thai M. Nguyen
- G01 - MEASURING TESTING
Information Patent Application
Method of generating an efficient stuck-at fault and transition del...
- Publication number 20050125755
- Publication date Jun 9, 2005
- Cam L. Lu
- G01 - MEASURING TESTING

Thai Minh Nguyen

Person

Patents Grantslast 30 patents

Closed-loop adaptive voltage scaling for integrated circuits

Testing a circuit with compressed scan chain subsets

On-chip circuit for transition delay fault test pattern generation...

Test clocking scheme

Method of generating an efficient stuck-at fault and transition del...

Method and apparatus for testing integrated circuit core modules

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF ADVANCED TRAFFIC MANAGEMENT

CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS

ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT ID...

ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION...

TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS

Method of testing scan chain integrity and tester setup for scan bl...

Test clocking scheme

Method of generating an efficient stuck-at fault and transition del...