Theo Drane

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient dual-path floating-point arithmetic operators
- Patent number 12,079,590
- Issue date Sep 3, 2024
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LEVEL-OF-DETAIL EIGENVECTOR DETERMINATION IN A GRAPHICS ENVIRONMENT
- Publication number 20240312110
- Publication date Sep 19, 2024
- Intel Corporation
- William ZORN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUTATIVE 1ULP HARDWARE MULTIPLIER
- Publication number 20240311083
- Publication date Sep 19, 2024
- Intel Corporation
- Theo Alan Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL-OF-DETAIL DETERMINATION USING MAJOR SQUARED AND EFFICIENT CLA...
- Publication number 20240312034
- Publication date Sep 19, 2024
- Intel Corporation
- William ZORN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD, AND COMPUTER-READABLE MEDIUM FOR FORMAL VERIFICATIO...
- Publication number 20240220703
- Publication date Jul 4, 2024
- Samuel COWARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, Device, Method and Computer Program for Generating an RT...
- Publication number 20240169133
- Publication date May 23, 2024
- Theo DRANE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATION OF CORRECTLY ROUNDED FLOATING POINT SUMMATION
- Publication number 20240160405
- Publication date May 16, 2024
- Intel Corporation
- Brett SAIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGER SQUARE 1ULP HARDWARE MULTIPLIER
- Publication number 20240160407
- Publication date May 16, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTATION OF EXACT FLOATING POINT ADDITION
- Publication number 20240152323
- Publication date May 9, 2024
- Intel Corporation
- Brett SAIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT N-INPUT SUM OF SQUARES 1ULP HARDWARE
- Publication number 20240143279
- Publication date May 2, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTANT MODULO VIA RECIRCULANT REDUCTION
- Publication number 20240134604
- Publication date Apr 25, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL...
- Publication number 20240135076
- Publication date Apr 25, 2024
- Intel Corporation
- Jianyi Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION
- Publication number 20240134603
- Publication date Apr 25, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER OPTIMIZED BLEND
- Publication number 20240126357
- Publication date Apr 18, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM ANALYSIS, DESIGN SPACE EXPLORATION AND VERIFICATION FOR HIG...
- Publication number 20240126519
- Publication date Apr 18, 2024
- Intel Corporation
- Jianyi Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED DETECTION OF CASE-SPLITTING OPPORTUNITIES IN RTL
- Publication number 20240126964
- Publication date Apr 18, 2024
- Intel Corporation
- Samuel Coward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS
- Publication number 20240126967
- Publication date Apr 18, 2024
- Intel Corporation
- Disha Puri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING
- Publication number 20240111353
- Publication date Apr 4, 2024
- Intel Corporation
- Samuel Coward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE POWER OPTIMIZATION VIA E-GRAPH BASED AUTOMATIC RTL EXPLORA...
- Publication number 20240111925
- Publication date Apr 4, 2024
- Intel Corporation
- Samuel Coward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT
- Publication number 20240111826
- Publication date Apr 4, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC CODE GENERATION OF OPTIMIZED RTL VIA REDUNDANT CODE REMOVAL
- Publication number 20240086161
- Publication date Mar 14, 2024
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING IN FLOATING POINT FUSED MULTIPLY-ADD OPERATIONS
- Publication number 20230205489
- Publication date Jun 29, 2023
- Intel Corporation
- Theo Drane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL OF DETAIL DETERMINATION
- Publication number 20220406000
- Publication date Dec 22, 2022
- Intel Corporation
- Theo DRANE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, Device, Method, and Computer Program for Generating a Re...
- Publication number 20220366112
- Publication date Nov 17, 2022
- Intel Corporation
- Theo DRANE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, Device, Method and Computer Program for Generating a Cir...
- Publication number 20220222413
- Publication date Jul 14, 2022
- Intel Corporation
- Theo DRANE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Dual-path Floating-Point Arithmetic Operators
- Publication number 20220206747
- Publication date Jun 30, 2022
- Intel Corporation
- Martin Langhammer
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Efficient dual-path floating-point arithmetic operators

Patents Applicationslast 30 patents

LEVEL-OF-DETAIL EIGENVECTOR DETERMINATION IN A GRAPHICS ENVIRONMENT

COMMUTATIVE 1ULP HARDWARE MULTIPLIER

LEVEL-OF-DETAIL DETERMINATION USING MAJOR SQUARED AND EFFICIENT CLA...

DEVICE, METHOD, AND COMPUTER-READABLE MEDIUM FOR FORMAL VERIFICATIO...

Apparatus, Device, Method and Computer Program for Generating an RT...

COMPUTATION OF CORRECTLY ROUNDED FLOATING POINT SUMMATION

INTEGER SQUARE 1ULP HARDWARE MULTIPLIER

COMPUTATION OF EXACT FLOATING POINT ADDITION

FLOATING-POINT N-INPUT SUM OF SQUARES 1ULP HARDWARE

CONSTANT MODULO VIA RECIRCULANT REDUCTION

SUPER-OPTIMIZATION EXPLORER USING E-GRAPH REWRITING FOR HIGH-LEVEL...

CONSTANT DIVISION AND MODULO VIA CARRYSAVE MODULO REDUCTION

POWER OPTIMIZED BLEND

PROGRAM ANALYSIS, DESIGN SPACE EXPLORATION AND VERIFICATION FOR HIG...

AUTOMATED DETECTION OF CASE-SPLITTING OPPORTUNITIES IN RTL

SEMI-AUTOMATIC TOOL TO CREATE FORMAL VERIFICATION MODELS

CONSTRUCTING HIERARCHICAL CLOCK GATING ARCHITECTURES VIA REWRITING

HARDWARE POWER OPTIMIZATION VIA E-GRAPH BASED AUTOMATIC RTL EXPLORA...

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

AUTOMATIC CODE GENERATION OF OPTIMIZED RTL VIA REDUNDANT CODE REMOVAL

PROCESSING IN FLOATING POINT FUSED MULTIPLY-ADD OPERATIONS

LEVEL OF DETAIL DETERMINATION

Apparatus, Device, Method, and Computer Program for Generating a Re...

Apparatus, Device, Method and Computer Program for Generating a Cir...

Efficient Dual-path Floating-Point Arithmetic Operators