Thierry Pons

Person

Hadera, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient implementation of complex vector fused multiply add and c...
- Patent number 11,455,167
- Issue date Sep 27, 2022
- Intel Coporation
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of complex vector fused multiply add and c...
- Patent number 10,521,226
- Issue date Dec 31, 2019
- Intel Corporation
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for early underflow detection and rounder bypass
- Patent number 10,157,059
- Issue date Dec 18, 2018
- Intel Corporation
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fused multiply add operations using bit masks
- Patent number 9,542,154
- Issue date Jan 10, 2017
- Intel Corporation
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leading change anticipator logic
- Patent number 9,274,752
- Issue date Mar 1, 2016
- Intel Corporation
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient parallel floating point exception handling in a processor
- Patent number 9,092,226
- Issue date Jul 28, 2015
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing power consumption in multi-precision floating point multip...
- Patent number 8,918,446
- Issue date Dec 23, 2014
- Intel Corporation
- Brent R. Boswell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient parallel floating point exception handling in a processor
- Patent number 8,103,858
- Issue date Jan 24, 2012
- Intel Corporation
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having inactive state of operation and method thereof
- Patent number 7,536,485
- Issue date May 19, 2009
- Intel Corporation
- Gila Kamhi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND C...
- Publication number 20200201628
- Publication date Jun 25, 2020
- Intel Corporation
- Raanan SADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND C...
- Publication number 20190303142
- Publication date Oct 3, 2019
- Intel Corporation
- Raanan SADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Early Underflow Detection and Rounder Bypass
- Publication number 20180088940
- Publication date Mar 29, 2018
- Intel Corporation
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUSED MULTIPLY ADD OPERATIONS USING BIT MASKS
- Publication number 20140379773
- Publication date Dec 25, 2014
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leading Change Anticipator Logic
- Publication number 20140188967
- Publication date Jul 3, 2014
- Simon Rubanovich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING POWER CONSUMPTION IN MULTI-PRECISION FLOATING POINT MULTIP...
- Publication number 20120151191
- Publication date Jun 14, 2012
- Brent R. Boswell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Parallel Floating Point Exception Handling In A Processor
- Publication number 20120084533
- Publication date Apr 5, 2012
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient parallel floating point exception handling in a processor
- Publication number 20090327665
- Publication date Dec 31, 2009
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor having inactive state of operation and method thereof
- Publication number 20070174589
- Publication date Jul 26, 2007
- Gila Kamhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System, apparatus and method of executing a micro operation
- Publication number 20070005940
- Publication date Jan 4, 2007
- Zeev Sperber
- G06 - COMPUTING CALCULATING COUNTING

Thierry Pons

Person

Patents Grantslast 30 patents

Efficient implementation of complex vector fused multiply add and c...

Efficient implementation of complex vector fused multiply add and c...

Instruction and logic for early underflow detection and rounder bypass

Fused multiply add operations using bit masks

Leading change anticipator logic

Efficient parallel floating point exception handling in a processor

Reducing power consumption in multi-precision floating point multip...

Efficient parallel floating point exception handling in a processor

Processor having inactive state of operation and method thereof

Patents Applicationslast 30 patents

EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND C...

EFFICIENT IMPLEMENTATION OF COMPLEX VECTOR FUSED MULTIPLY ADD AND C...

Instruction and Logic for Early Underflow Detection and Rounder Bypass

FUSED MULTIPLY ADD OPERATIONS USING BIT MASKS

Leading Change Anticipator Logic

REDUCING POWER CONSUMPTION IN MULTI-PRECISION FLOATING POINT MULTIP...

Efficient Parallel Floating Point Exception Handling In A Processor

Efficient parallel floating point exception handling in a processor

Processor having inactive state of operation and method thereof

System, apparatus and method of executing a micro operation