Thomas Alan Ziaja

Person

Pflugerville, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scannable memory array and a method for scanning memory
- Patent number 12,243,604
- Issue date Mar 4, 2025
- SambaNova Systems, Inc.
- Thomas Ziaja
- G11 - INFORMATION STORAGE
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Built-in self-test for processor unit with combined memory and logic
- Patent number 11,449,404
- Issue date Sep 20, 2022
- SambaNova Systems, Inc.
- Thomas Alan Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for scan dump of latch array
- Patent number 11,443,823
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for row scannable latch array
- Patent number 11,443,822
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array of processor units with local BIST
- Patent number 11,428,737
- Issue date Aug 30, 2022
- SambaNova Systems, Inc.
- Thomas Alan Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit march testing
- Patent number 10,408,876
- Issue date Sep 10, 2019
- Oracle International Corporation
- Thomas Ziaja
- G01 - MEASURING TESTING
Information Patent Grant
At-speed test of memory arrays using scan
- Patent number 9,401,223
- Issue date Jul 26, 2016
- Oracle International Corporation
- Thomas A Ziaja
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing multi-core processors
- Patent number 8,214,703
- Issue date Jul 3, 2012
- Oracle America, Inc.
- Murali Mohan Reddy Gala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing delay faults
- Patent number 8,074,133
- Issue date Dec 6, 2011
- Oracle America, Inc.
- Thomas A. Ziaja
- G01 - MEASURING TESTING
Information Patent Grant
At-speed scan testing of memory arrays
- Patent number 8,065,572
- Issue date Nov 22, 2011
- Oracle America, Inc.
- Thomas A. Ziaja
- G11 - INFORMATION STORAGE
Information Patent Grant
Enabling on-chip features via efuses
- Patent number 7,795,899
- Issue date Sep 14, 2010
- Oracle America, Inc.
- Gregory F. Grohoski
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with blocking pin to coordinate entry into test...
- Patent number 7,657,805
- Issue date Feb 2, 2010
- Sun Microsystems, Inc.
- Thomas Alan Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with embedded test functionality
- Patent number 7,657,807
- Issue date Feb 2, 2010
- Sun Microsystems, Inc.
- Daniel R. Watkins
- G01 - MEASURING TESTING
Information Patent Grant
Automatic generation and validation of memory test models
- Patent number 6,813,201
- Issue date Nov 2, 2004
- Sun Microsystems, Inc.
- Kamran Zarrineh
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Fully Scannable Memory Arrays
- Publication number 20240412797
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Scanning a Memory Array
- Publication number 20240412798
- Publication date Dec 12, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20230005560
- Publication date Jan 5, 2023
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY
- Publication number 20220139477
- Publication date May 5, 2022
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAY
- Publication number 20220139478
- Publication date May 5, 2022
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT MARCH TESTING
- Publication number 20190235019
- Publication date Aug 1, 2019
- Oracle International Corporation
- Thomas Ziaja
- G01 - MEASURING TESTING
Information Patent Application
At-Speed Test of Memory Arrays Using Scan
- Publication number 20150325314
- Publication date Nov 12, 2015
- Thomas A Ziaja
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED SCAN TESTING OF MEMORY ARRAYS
- Publication number 20100332924
- Publication date Dec 30, 2010
- Thomas A. Ziaja
- G01 - MEASURING TESTING
Information Patent Application
TESTING MULTI-CORE PROCESSORS
- Publication number 20100235683
- Publication date Sep 16, 2010
- SUN MICROSYSTEMS, INC.
- Murali Mohan Reddy Gala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TESTING DELAY FAULTS
- Publication number 20100037111
- Publication date Feb 11, 2010
- SUN MICROSYSTEMS, INC.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST...
- Publication number 20090013224
- Publication date Jan 8, 2009
- Thomas Alan Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic generation and validation of memory test models
- Publication number 20030076723
- Publication date Apr 24, 2003
- SUN MICROSYSTEMS, INC.
- Kamran Zarrineh
- G11 - INFORMATION STORAGE

Thomas Alan Ziaja

Person

Patents Grantslast 30 patents

Scannable memory array and a method for scanning memory

Single “A” latch with an array of “B” latches

Built-in self-test for processor unit with combined memory and logic

Method and circuit for scan dump of latch array

Method and circuit for row scannable latch array

Array of processor units with local BIST

Memory circuit march testing

At-speed test of memory arrays using scan

Testing multi-core processors

Method and apparatus for testing delay faults

At-speed scan testing of memory arrays

Enabling on-chip features via efuses

Integrated circuit with blocking pin to coordinate entry into test...

Integrated circuit with embedded test functionality

Automatic generation and validation of memory test models

Patents Applicationslast 30 patents

Fully Scannable Memory Arrays

Method for Scanning a Memory Array

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY

METHOD AND CIRCUIT FOR SCAN DUMP OF LATCH ARRAY

MEMORY CIRCUIT MARCH TESTING

At-Speed Test of Memory Arrays Using Scan

AT-SPEED SCAN TESTING OF MEMORY ARRAYS

TESTING MULTI-CORE PROCESSORS

METHOD AND APPARATUS FOR TESTING DELAY FAULTS

INTEGRATED CIRCUIT WITH BLOCKING PIN TO COORDINATE ENTRY INTO TEST...

Automatic generation and validation of memory test models