Thomas Andrew Newton

Person

Great Cambourne, GB

People

Patents Grantslast 30 patents

Information Patent Grant
User interface for interactive skew group analysis
- Patent number 11,620,417
- Issue date Apr 4, 2023
- Cadence Design Systems, Inc.
- Ainsley Malcolm Pereira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generate clock network using inverting integrated clock gate
- Patent number 11,163,929
- Issue date Nov 2, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using negative-edge integrated clock gate in clock network
- Patent number 11,132,490
- Issue date Sep 28, 2021
- Cadence Design Systems, Inc.
- Ruth Patricia Jackson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay dependence in physically aware cell cloning
- Patent number 10,990,721
- Issue date Apr 27, 2021
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-dimension clock gate design in clock tree synthesis
- Patent number 10,963,618
- Issue date Mar 30, 2021
- Cadence Design Systems, Ine.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock gate placement with data path awareness
- Patent number 10,885,250
- Issue date Jan 5, 2021
- Cadence Design Systems, Inc.
- David White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Route driven placement of fan-out clock drivers
- Patent number 10,740,532
- Issue date Aug 11, 2020
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region aware clustering
- Patent number 10,402,522
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of cells in a multi-level routing tree
- Patent number 10,402,533
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- William Robert Reece
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for clock tree generation with buffers and inve...
- Patent number 10,354,040
- Issue date Jul 16, 2019
- Cadence Design Systems, Inc.
- Amin Farshidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced scaled-load clustering
- Patent number 10,318,693
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local cluster refinement
- Patent number 10,289,797
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing tree topology generation
- Patent number 10,289,795
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Jhih-Rong Gao
- G06 - COMPUTING CALCULATING COUNTING

Thomas Andrew Newton

Person

Patents Grantslast 30 patents

User interface for interactive skew group analysis

Generate clock network using inverting integrated clock gate

Using negative-edge integrated clock gate in clock network

Delay dependence in physically aware cell cloning

Multi-dimension clock gate design in clock tree synthesis

Clock gate placement with data path awareness

Route driven placement of fan-out clock drivers

Region aware clustering

Placement of cells in a multi-level routing tree

Systems and methods for clock tree generation with buffers and inve...

Balanced scaled-load clustering

Local cluster refinement

Routing tree topology generation