Thomas Böhm

Person

Zorneding, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory device having a plurality of memory areas with...
- Patent number 7,158,405
- Issue date Jan 2, 2007
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM configuration having selection transistors with a large channe...
- Patent number 6,803,618
- Issue date Oct 12, 2004
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having row and column redundancy circui...
- Patent number 6,618,306
- Issue date Sep 9, 2003
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM module configuration
- Patent number 6,545,900
- Issue date Apr 8, 2003
- Infineon Technologies, AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory and corresponding operating method
- Patent number 6,538,950
- Issue date Mar 25, 2003
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with redundancy
- Patent number 6,525,974
- Issue date Feb 25, 2003
- Infineon Technologies AG
- Ernst Neuhold
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells and reference cells, and oper...
- Patent number 6,487,128
- Issue date Nov 26, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Current driver configuration for MRAM
- Patent number 6,483,768
- Issue date Nov 19, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoder element for generating an output signal having three differ...
- Patent number 6,480,055
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell configuration and corresponding production process
- Patent number 6,472,696
- Issue date Oct 29, 2002
- Infineon Technologies AG
- Ulrich Zimmermann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MRAM configuration
- Patent number 6,473,335
- Issue date Oct 29, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells and reference cells, and corr...
- Patent number 6,459,626
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory configuration with a refresh logic circuit, an...
- Patent number 6,452,852
- Issue date Sep 17, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory
- Patent number 6,442,100
- Issue date Aug 27, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS voltage divider
- Patent number 6,429,731
- Issue date Aug 6, 2002
- Infineon Technologies AG
- Thomas Böhm
- G05 - CONTROLLING REGULATING
Information Patent Grant
Decoder element for producing an output signal having three differe...
- Patent number 6,392,445
- Issue date May 21, 2002
- Infineon Technologies AG
- Thomas Röhr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated semiconductor memory with redundant units for memory cells
- Patent number 6,353,562
- Issue date Mar 5, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having a differential sense amplifier
- Patent number 6,351,422
- Issue date Feb 26, 2002
- Infineon Technologies AG
- Thomas Röhr
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell configuration and corresponding fabrication method
- Patent number 6,258,658
- Issue date Jul 10, 2001
- Infineon Technologies AG
- Thomas Böhm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated memory having sense amplifiers disposed on opposite side...
- Patent number 6,259,641
- Issue date Jul 10, 2001
- Infineon Technologies AG
- Zoltan Manyoki
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a decoder
- Patent number 6,255,855
- Issue date Jul 3, 2001
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MRAM configuration having selection transistors with a large channe...
- Publication number 20030218926
- Publication date Nov 27, 2003
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Digital memory circuit and method of manufacturing the circuit
- Publication number 20030039157
- Publication date Feb 27, 2003
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20030007382
- Publication date Jan 9, 2003
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM module configuration
- Publication number 20020075718
- Publication date Jun 20, 2002
- Thomas Bohm
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated memory having memory cells and reference cells, and corr...
- Publication number 20020071317
- Publication date Jun 13, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory and corresponding operating method
- Publication number 20020044493
- Publication date Apr 18, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having memory cells and reference cells, and oper...
- Publication number 20020027816
- Publication date Mar 7, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Current driver configuration for MRAM
- Publication number 20020024875
- Publication date Feb 28, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory with redundancy
- Publication number 20020015337
- Publication date Feb 7, 2002
- Ernst Neuhold
- G11 - INFORMATION STORAGE
Information Patent Application
Decoder element for generating an output signal having three differ...
- Publication number 20020008564
- Publication date Jan 24, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM configuration
- Publication number 20020003720
- Publication date Jan 10, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory
- Publication number 20020003735
- Publication date Jan 10, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having a differential sense amplifier
- Publication number 20010038562
- Publication date Nov 8, 2001
- Thomas Rohr
- G11 - INFORMATION STORAGE
Information Patent Application
CMOS voltage divider
- Publication number 20010030573
- Publication date Oct 18, 2001
- Thomas Böhm
- G05 - CONTROLLING REGULATING
Information Patent Application
Decoder element for producing an output signal having three differe...
- Publication number 20010026485
- Publication date Oct 4, 2001
- Thomas Rohr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor memory configuration with a refresh logic circuit, an...
- Publication number 20010026491
- Publication date Oct 4, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having a bit line reference voltage, and a method...
- Publication number 20010024396
- Publication date Sep 27, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory with redundant units for memory cells
- Publication number 20010021134
- Publication date Sep 13, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE

Thomas Böhm

Person

Patents Grantslast 30 patents

Semiconductor memory device having a plurality of memory areas with...

MRAM configuration having selection transistors with a large channe...

Semiconductor memory device having row and column redundancy circui...

MRAM module configuration

Integrated memory and corresponding operating method

Integrated memory with redundancy

Integrated memory having memory cells and reference cells, and oper...

Current driver configuration for MRAM

Decoder element for generating an output signal having three differ...

Memory cell configuration and corresponding production process

MRAM configuration

Integrated memory having memory cells and reference cells, and corr...

Semiconductor memory configuration with a refresh logic circuit, an...

Integrated memory

CMOS voltage divider

Decoder element for producing an output signal having three differe...

Integrated semiconductor memory with redundant units for memory cells

Integrated memory having a differential sense amplifier

Memory cell configuration and corresponding fabrication method

Integrated memory having sense amplifiers disposed on opposite side...

Integrated circuit having a decoder

Patents Applicationslast 30 patents

MRAM configuration having selection transistors with a large channe...

Digital memory circuit and method of manufacturing the circuit

Semiconductor memory device

MRAM module configuration

Integrated memory having memory cells and reference cells, and corr...

Integrated memory and corresponding operating method

Integrated memory having memory cells and reference cells, and oper...

Current driver configuration for MRAM

Integrated memory with redundancy

Decoder element for generating an output signal having three differ...

MRAM configuration

Integrated memory

Integrated memory having a differential sense amplifier

CMOS voltage divider

Decoder element for producing an output signal having three differe...

Semiconductor memory configuration with a refresh logic circuit, an...

Integrated memory having a bit line reference voltage, and a method...

Integrated semiconductor memory with redundant units for memory cells