Thomas Chadwick

Person

Essex, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for enumerating digital circuits in a system-on-a...
- Patent number 10,628,375
- Issue date Apr 21, 2020
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for enumerating digital circuits in a system-on-a...
- Patent number 10,628,376
- Issue date Apr 21, 2020
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for enumerating digital circuits in a system-on-a...
- Patent number 10,423,570
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for enumerating digital circuits in a system-on-a...
- Patent number 10,394,752
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory built-in self test system
- Patent number 9,946,620
- Issue date Apr 17, 2018
- Invecas, Inc.
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Diagnostics for a memory device
- Patent number 9,865,361
- Issue date Jan 9, 2018
- Invecas, Inc.
- Thomas Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-domain fuse management
- Patent number 9,799,413
- Issue date Oct 24, 2017
- Invecas, Inc.
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for enumerating digital circuits in a system-on-a...
- Patent number 9,672,185
- Issue date Jun 6, 2017
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shadow registers for least recently used data in cache
- Patent number 8,667,223
- Issue date Mar 4, 2014
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus of local word-line redundancy in CAM
- Patent number 6,920,525
- Issue date Jul 19, 2005
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Saving content addressable memory power through conditional compari...
- Patent number 6,711,040
- Issue date Mar 23, 2004
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Saving content addressable memory power through conditional compari...
- Patent number 6,552,920
- Issue date Apr 22, 2003
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded CAM test structure for fully testing all matchlines
- Patent number 6,430,072
- Issue date Aug 6, 2002
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory device
- Patent number 6,341,079
- Issue date Jan 22, 2002
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ON-CHIP AUTOMATION OF CLOCK-TO-Q ACCESS TIME MEASUREMENT OF A MEMOR...
- Publication number 20230352069
- Publication date Nov 2, 2023
- Synopsys, Inc.
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...
- Publication number 20190332570
- Publication date Oct 31, 2019
- International Business Machines Corporation
- Thomas B. CHADWICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...
- Publication number 20190332571
- Publication date Oct 31, 2019
- International Business Machines Corporation
- Thomas B. CHADWICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Diagnostics for a Memory Device
- Publication number 20170316837
- Publication date Nov 2, 2017
- Invecas, Inc.
- Thomas Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...
- Publication number 20170161225
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Thomas B. CHADWICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...
- Publication number 20170161229
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Thomas B. CHADWICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Domain Fuse Management
- Publication number 20160224451
- Publication date Aug 4, 2016
- Invecas, Inc.
- Kevin W. Gorman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Built-In Self Test System
- Publication number 20160224450
- Publication date Aug 4, 2016
- Invecas, Inc.
- Kevin W. Gorman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...
- Publication number 20150095541
- Publication date Apr 2, 2015
- International Business Machines Corporation
- Thomas B. CHADWICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHADOW REGISTERS FOR LEAST RECENTLY USED DATA IN CACHE
- Publication number 20130042068
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
- Publication number 20080270962
- Publication date Oct 30, 2008
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
- Publication number 20070226667
- Publication date Sep 27, 2007
- Thomas B. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus of local word-line redundancy in CAM
- Publication number 20040015651
- Publication date Jan 22, 2004
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
Saving content addressable memory power through conditional compari...
- Publication number 20030112648
- Publication date Jun 19, 2003
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
Saving content addressable memory power through conditional compari...
- Publication number 20030002313
- Publication date Jan 2, 2003
- International Business Machines Corporation
- Thomas B. Chadwick
- G11 - INFORMATION STORAGE

Thomas Chadwick

Person

Patents Grantslast 30 patents

Method and system for enumerating digital circuits in a system-on-a...

Method and system for enumerating digital circuits in a system-on-a...

Method and system for enumerating digital circuits in a system-on-a...

Method and system for enumerating digital circuits in a system-on-a...

Memory built-in self test system

Diagnostics for a memory device

Multi-domain fuse management

Method and system for enumerating digital circuits in a system-on-a...

Shadow registers for least recently used data in cache

Method and apparatus of local word-line redundancy in CAM

Saving content addressable memory power through conditional compari...

Saving content addressable memory power through conditional compari...

Embedded CAM test structure for fully testing all matchlines

Content addressable memory device

Patents Applicationslast 30 patents

ON-CHIP AUTOMATION OF CLOCK-TO-Q ACCESS TIME MEASUREMENT OF A MEMOR...

METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...

METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...

Diagnostics for a Memory Device

METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...

METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...

Multi-Domain Fuse Management

Memory Built-In Self Test System

METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A...

SHADOW REGISTERS FOR LEAST RECENTLY USED DATA IN CACHE

STATIC TIMING SLACKS ANALYSIS AND MODIFICATION

STATIC TIMING SLACKS ANALYSIS AND MODIFICATION

Method and apparatus of local word-line redundancy in CAM

Saving content addressable memory power through conditional compari...

Saving content addressable memory power through conditional compari...