Thomas Evan Wilson

Person

Laurel, MD, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamically updated delay line
- Patent number 11,876,521
- Issue date Jan 16, 2024
- Cadence Design Systems, Inc.
- Hajee Mohammed Shuaeb Fazeel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sampler with built-in DFE and offset cancellation
- Patent number 11,677,593
- Issue date Jun 13, 2023
- Cadence Design Systems, Inc.
- Vinod Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reference voltage training scheme
- Patent number 11,580,048
- Issue date Feb 14, 2023
- Cadence Designs Systems, Inc.
- Thomas E. Wilson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active suppression circuitry
- Patent number 11,545,968
- Issue date Jan 3, 2023
- Cadence Design Systems, Inc.
- Moo Sung Chae
- G11 - INFORMATION STORAGE
Information Patent Grant
Slew rate boosting for communication interfaces
- Patent number 11,481,148
- Issue date Oct 25, 2022
- Cadence Design Systems, Inc.
- Vinod Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware efficient decision feedback equalization training
- Patent number 11,483,185
- Issue date Oct 25, 2022
- Cadence Design Systems, Inc.
- Sachin Ramesh Gugwad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Decision feedback equalization training scheme for GDDR applications
- Patent number 11,323,296
- Issue date May 3, 2022
- Cadence Design Systems, Inc.
- Sachin Ramesh Gugwad
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Time-based decision feedback equalizer
- Patent number 10,958,484
- Issue date Mar 23, 2021
- Cadence Design Systems, Inc.
- Hajee Mohammed Shuaeb Fazeel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed low VT drift receiver
- Patent number 10,705,984
- Issue date Jul 7, 2020
- Cadence Design Systems, Inc.
- H Md Shuaeb Fazeel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protocol compliant high-speed DDR transmitter
- Patent number 10,566,046
- Issue date Feb 18, 2020
- Cadence Design Systems, Inc.
- Vinod Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Auto-zeroing receiver for memory interface devices
- Patent number 10,545,895
- Issue date Jan 28, 2020
- Cadence Design Systems, Inc.
- Aaron Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed low VT drift receiver
- Patent number 10,545,889
- Issue date Jan 28, 2020
- Cadence Design Systems, Inc.
- H Md Shuaeb Fazeel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual path phase-locked loop circuit
- Patent number 10,389,368
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Fuyue Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast settling bias circuit
- Patent number 10,345,845
- Issue date Jul 9, 2019
- Cadence Design Systems, Inc.
- Ling Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for a memory interface receiver
- Patent number 10,193,555
- Issue date Jan 29, 2019
- Cadence Design Systems, Inc.
- Eric Harris Naviasky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency to current circuit
- Patent number 10,161,974
- Issue date Dec 25, 2018
- Cadence Design Systems, Inc.
- Ling Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Coupled inverter with auto-calibration
- Patent number 10,128,965
- Issue date Nov 13, 2018
- Cadence Design Systems, Inc.
- Thomas E. Wilson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and devices for high-sensitivity memory interface receiver
- Patent number 9,767,888
- Issue date Sep 19, 2017
- Cadence Design Systems, Inc.
- Hari Anand Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage stress tolerant high speed memory driver having flying capa...
- Patent number 9,754,646
- Issue date Sep 5, 2017
- Cadence Design Systems, Inc.
- Vinod Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and devices for a DDR memory driver using a voltage transla...
- Patent number 9,589,627
- Issue date Mar 7, 2017
- Cadence Design Systems, Inc.
- Thomas Evan Wilson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for synchronously adjusted delay and distortion m...
- Patent number 9,405,314
- Issue date Aug 2, 2016
- Cadence Design Systems, Inc.
- Eric Naviasky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog-to-digital converter based decision feedback equalization
- Patent number 8,737,490
- Issue date May 27, 2014
- Cadence Design Systems, Inc.
- Thomas Evan Wilson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Analog-to-digital converter based decision feedback equalization
- Patent number 8,737,491
- Issue date May 27, 2014
- Cadence Design Systems, Inc.
- Thomas Evan Wilson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods of clock signal generation with selected phase delay
- Patent number 8,502,586
- Issue date Aug 6, 2013
- Cadence Design Systems, Inc.
- Eric Naviasky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase interpolator circuit with two phase capacitor charging
- Patent number 8,063,686
- Issue date Nov 22, 2011
- Cadence Design Systems, Inc.
- Eric Naviasky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clipped dynamic range compression image sensing apparatus
- Patent number 5,164,832
- Issue date Nov 17, 1992
- Westinghouse Electric Corp.
- James Halvis
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Thomas Evan Wilson

Person

Patents Grantslast 30 patents

Dynamically updated delay line

Sampler with built-in DFE and offset cancellation

Reference voltage training scheme

Active suppression circuitry

Slew rate boosting for communication interfaces

Hardware efficient decision feedback equalization training

Decision feedback equalization training scheme for GDDR applications

Time-based decision feedback equalizer

High-speed low VT drift receiver

Protocol compliant high-speed DDR transmitter

Auto-zeroing receiver for memory interface devices

High-speed low VT drift receiver

Dual path phase-locked loop circuit

Fast settling bias circuit

Methods and devices for a memory interface receiver

Frequency to current circuit

Coupled inverter with auto-calibration

Methods and devices for high-sensitivity memory interface receiver

Voltage stress tolerant high speed memory driver having flying capa...

Methods and devices for a DDR memory driver using a voltage transla...

System and method for synchronously adjusted delay and distortion m...

Analog-to-digital converter based decision feedback equalization

Analog-to-digital converter based decision feedback equalization

Methods of clock signal generation with selected phase delay

Phase interpolator circuit with two phase capacitor charging

Clipped dynamic range compression image sensing apparatus