Thomas Hans Rinderknecht

Person

Tualatin, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scan test application through high-speed serial input/outputs
- Patent number 8,726,112
- Issue date May 13, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Performance of signature-based diagnosis for logic BIST
- Patent number 8,448,032
- Issue date May 21, 2013
- Mentor Graphics Corporation
- Manish Sharma
- G01 - MEASURING TESTING
Information Patent Grant
High speed clock control
- Patent number 8,448,008
- Issue date May 21, 2013
- Mentor Graphics Corporation
- Friedrich Hapke
- G01 - MEASURING TESTING
Information Patent Grant
Direct fault diagnostics using per-pattern compactor signatures
- Patent number 8,280,687
- Issue date Oct 2, 2012
- Mentor Graphics Corporation
- Wu-Tung Cheng
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-test of integrated circuits using selectable weightin...
- Patent number 7,840,865
- Issue date Nov 23, 2010
- Mentor Graphics Corporation
- Liyang Lai
- G01 - MEASURING TESTING
Information Patent Grant
Restartable logic BIST controller
- Patent number 7,644,333
- Issue date Jan 5, 2010
- Christopher John Hill
- G01 - MEASURING TESTING
Information Patent Grant
Using constrained scan cells to test integrated circuits
- Patent number 7,296,249
- Issue date Nov 13, 2007
- Thomas Hans Rinderknecht
- G01 - MEASURING TESTING
Information Patent Grant
Uniform testing of tristate nets in logic BIST
- Patent number 6,920,597
- Issue date Jul 19, 2005
- Thomas Hans Rinderknecht
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
The Performance Of Signature-Based Diagnosis For Logic BIST
- Publication number 20110179326
- Publication date Jul 21, 2011
- Mentor Graphics Corporation
- Manish Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Test Application Through High-Speed Serial Input/Outputs
- Publication number 20100313089
- Publication date Dec 9, 2010
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
High Speed Clock Control
- Publication number 20100251045
- Publication date Sep 30, 2010
- Mentor Graphics Corporation
- Friedrich HAPKE
- G01 - MEASURING TESTING
Information Patent Application
Built-in self-test of integrated circuits using selectable weightin...
- Publication number 20080235544
- Publication date Sep 25, 2008
- Mentor Graphics Corporation
- Liyang Lai
- G01 - MEASURING TESTING
Information Patent Application
Using constrained scan cells to test integrated circuits
- Publication number 20080201670
- Publication date Aug 21, 2008
- Thomas Hans Rinderknecht
- G01 - MEASURING TESTING
Information Patent Application
Direct fault diagnostics using per-pattern compactor signatures
- Publication number 20070100586
- Publication date May 3, 2007
- Wu-Tung Cheng
- G01 - MEASURING TESTING
Information Patent Application
Using constrained scan cells to test integrated circuits
- Publication number 20050081130
- Publication date Apr 14, 2005
- Mentor Graphics Corporation
- Thomas Hans Rinderknecht
- G01 - MEASURING TESTING
Information Patent Application
Uniform testing of tristate nets in logic BIST
- Publication number 20040025096
- Publication date Feb 5, 2004
- Thomas Hans Rinderknecht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Restartable logic bist controller
- Publication number 20030115525
- Publication date Jun 19, 2003
- Mentor Graphics Corporation
- Christopher John Hill
- G01 - MEASURING TESTING

Thomas Hans Rinderknecht

Person

Patents Grantslast 30 patents

Scan test application through high-speed serial input/outputs

Performance of signature-based diagnosis for logic BIST

High speed clock control

Direct fault diagnostics using per-pattern compactor signatures

Built-in self-test of integrated circuits using selectable weightin...

Restartable logic BIST controller

Using constrained scan cells to test integrated circuits

Uniform testing of tristate nets in logic BIST

Patents Applicationslast 30 patents

The Performance Of Signature-Based Diagnosis For Logic BIST

Scan Test Application Through High-Speed Serial Input/Outputs

High Speed Clock Control

Built-in self-test of integrated circuits using selectable weightin...

Using constrained scan cells to test integrated circuits

Direct fault diagnostics using per-pattern compactor signatures

Using constrained scan cells to test integrated circuits

Uniform testing of tristate nets in logic BIST

Restartable logic bist controller