Thomas J. De Bonis

Person

Tempe, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-chip packaging
- Patent number 11,817,444
- Issue date Nov 14, 2023
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-trenching mold interface in a pop package
- Patent number 11,462,527
- Issue date Oct 4, 2022
- Intel Corporation
- Kumar Abhishek Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip packaging
- Patent number 11,348,911
- Issue date May 31, 2022
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally coupled package-on-package semiconductor packages
- Patent number 11,222,877
- Issue date Jan 11, 2022
- Intel Corporation
- Omkar Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip packaging
- Patent number 10,700,051
- Issue date Jun 30, 2020
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure to enhance yield of TMI interconnections
- Patent number 10,049,971
- Issue date Aug 14, 2018
- Intel Corporation
- Thomas J. De Bonis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package structure to enhance yield of TMI interconnections
- Patent number 9,613,933
- Issue date Apr 4, 2017
- Intel Corporation
- Thomas J. De Bonis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Assembly packaging using induction heating
- Patent number 7,880,124
- Issue date Feb 1, 2011
- Intel Corporation
- Thomas Joseph DeBonis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Protective layer during scribing
- Patent number 7,265,032
- Issue date Sep 4, 2007
- Intel Corporation
- Sujit Sharan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Assembly packaging using induction heating
- Patent number 7,161,122
- Issue date Jan 9, 2007
- Intel Corporation
- Thomas Joseph DeBonis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
MULTI-CHIP PACKAGING
- Publication number 20240128256
- Publication date Apr 18, 2024
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGING
- Publication number 20220231007
- Publication date Jul 21, 2022
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGING
- Publication number 20220157803
- Publication date May 19, 2022
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGING
- Publication number 20200395352
- Publication date Dec 17, 2020
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-TRENCHING MOLD INTERFACE IN A POP PACKAGE
- Publication number 20200035658
- Publication date Jan 30, 2020
- Intel Corporation
- Kumar Abhishek SINGH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGING
- Publication number 20190371778
- Publication date Dec 5, 2019
- Intel Corporation
- Robert L. Sankman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMALLY COUPLED PACKAGE-ON-PACKAGE SEMICONDUCTOR
- Publication number 20190103385
- Publication date Apr 4, 2019
- Intel Corporation
- OMKAR KARHADE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE ARCHITECTURE FOR SOLDER JOINT RELIABILTY IN MICROELECTRON...
- Publication number 20190104610
- Publication date Apr 4, 2019
- Intel Corporation
- Robert Nickerson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Package Structure To Enhance Yield of TMI Interconnections
- Publication number 20170207152
- Publication date Jul 20, 2017
- Intel Corporation
- Thomas J. De Bonis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Package Structure To Enhance Yield of TMI Interconnections
- Publication number 20150255415
- Publication date Sep 10, 2015
- Thomas J. De Bonis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assembly packaging using induction heating
- Publication number 20070084856
- Publication date Apr 19, 2007
- Thomas Joseph DeBonis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Assembly packaging using induction heating
- Publication number 20050284863
- Publication date Dec 29, 2005
- Thomas Joseph DeBonis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Protective layer during scribing
- Publication number 20050070095
- Publication date Mar 31, 2005
- Sujit Sharan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Thomas J. De Bonis

Person

Patents Grantslast 30 patents

Multi-chip packaging

Micro-trenching mold interface in a pop package

Multi-chip packaging

Thermally coupled package-on-package semiconductor packages

Multi-chip packaging

Package structure to enhance yield of TMI interconnections

Package structure to enhance yield of TMI interconnections

Assembly packaging using induction heating

Protective layer during scribing

Assembly packaging using induction heating

Patents Applicationslast 30 patents

MULTI-CHIP PACKAGING

MULTI-CHIP PACKAGING

MULTI-CHIP PACKAGING

MULTI-CHIP PACKAGING

MICRO-TRENCHING MOLD INTERFACE IN A POP PACKAGE

MULTI-CHIP PACKAGING

THERMALLY COUPLED PACKAGE-ON-PACKAGE SEMICONDUCTOR

SUBSTRATE ARCHITECTURE FOR SOLDER JOINT RELIABILTY IN MICROELECTRON...

Package Structure To Enhance Yield of TMI Interconnections

Package Structure To Enhance Yield of TMI Interconnections

Assembly packaging using induction heating

Assembly packaging using induction heating

Protective layer during scribing