Thomas J. Knips

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing bit write operation to a memory array in integrated circuits
- Patent number 11,657,887
- Issue date May 23, 2023
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
Failing address registers for built-in self tests
- Patent number 11,081,202
- Issue date Aug 3, 2021
- International Business Machines Corporation
- Uma Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing multi-port array in integrated circuits
- Patent number 11,069,422
- Issue date Jul 20, 2021
- International Business Machines Corporation
- Matthew Steven Hyde
- G11 - INFORMATION STORAGE
Information Patent Grant
Partition-able storage of test results using inactive storage elements
- Patent number 9,983,261
- Issue date May 29, 2018
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Grant
Built-in testing of unused element on chip
- Patent number 9,355,746
- Issue date May 31, 2016
- International Business Machines Corporation
- Luiz C. Alves
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in testing of unused element on chip
- Patent number 9,136,019
- Issue date Sep 15, 2015
- International Business Machines Corporation
- Luiz C. Alves
- G11 - INFORMATION STORAGE
Information Patent Grant
AC ABIST diagnostic method, apparatus and program product
- Patent number 7,930,601
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Joseph Eckelman
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient memory product for test and soft repair of SRAM with redu...
- Patent number 7,793,173
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for self-correcting cache using line delete, data logging, a...
- Patent number 7,529,997
- Issue date May 5, 2009
- International Business Machines Corporation
- Patrick J. Meaney
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient method of test and soft repair of SRAM with redundancy
- Patent number 7,437,626
- Issue date Oct 14, 2008
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
ABIST data compression and serialization for memory built-in self t...
- Patent number 7,380,191
- Issue date May 27, 2008
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for providing flexible modular redundancy allo...
- Patent number 7,219,275
- Issue date May 15, 2007
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated system logic and ABIST data compression for an SRAM dire...
- Patent number 7,210,084
- Issue date Apr 24, 2007
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast pulse powered NOR decode apparatus with pulse stretching and r...
- Patent number 7,170,320
- Issue date Jan 30, 2007
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for ABIST diagnostics
- Patent number 7,076,706
- Issue date Jul 11, 2006
- International Business Machines Corporation
- Joseph E. Eckelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-binary address generation for ABIST
- Patent number 7,076,710
- Issue date Jul 11, 2006
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
ABIST address generation
- Patent number 7,073,105
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for implementing multiple memory redundancy wi...
- Patent number 7,068,554
- Issue date Jun 27, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for implementing multiple column redundancy fo...
- Patent number 7,064,990
- Issue date Jun 20, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for skip over redundancy decode with very low overhead
- Patent number 7,009,895
- Issue date Mar 7, 2006
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
System for implementing a column redundancy scheme for arrays with...
- Patent number 6,584,023
- Issue date Jun 24, 2003
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TESTING BIT WRITE OPERATION TO A MEMORY ARRAY IN INTEGRATED CIRCUITS
- Publication number 20230089274
- Publication date Mar 23, 2023
- International Business Machines Corporation
- Thomas J. KNIPS
- G11 - INFORMATION STORAGE
Information Patent Application
FAILING ADDRESS REGISTERS FOR BUILT-IN SELF TESTS
- Publication number 20210098069
- Publication date Apr 1, 2021
- International Business Machines Corporation
- UMA SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
PARTITION-ABLE STORAGE OF TEST RESULTS USING INACTIVE STORAGE ELEMENTS
- Publication number 20170350940
- Publication date Dec 7, 2017
- International Business Machines Corporation
- William V. Huott
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP
- Publication number 20150262711
- Publication date Sep 17, 2015
- International Business Machines Corporation
- Luiz C. Alves
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP
- Publication number 20150262713
- Publication date Sep 17, 2015
- International Business Machines Corporation
- Luiz C. Alves
- G11 - INFORMATION STORAGE
Information Patent Application
AC ABIST Diagnostic Method, Apparatus and Program Product
- Publication number 20090217112
- Publication date Aug 27, 2009
- International Business Machines Corporation
- Joseph Eckelman
- G11 - INFORMATION STORAGE
Information Patent Application
Efficient Memory Product for Test and Soft Repair of SRAM with Redu...
- Publication number 20080263417
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method for self-correcting cache using line delete, d...
- Publication number 20060203578
- Publication date Sep 14, 2006
- International Business Machines Corporation
- Patrick J. Meaney
- G11 - INFORMATION STORAGE
Information Patent Application
Efficient method of test and soft repair of SRAM with redundancy
- Publication number 20060181941
- Publication date Aug 17, 2006
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Fast pulse powered NOR decode apparatus with pulse stretching and r...
- Publication number 20060176194
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James W. Dawson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for providing flexible modular redundancy allo...
- Publication number 20060179368
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Tom Y. Chang
- G11 - INFORMATION STORAGE
Information Patent Application
ABIST data compression and serialization for memory built-in self t...
- Publication number 20060179377
- Publication date Aug 10, 2006
- International Business Machines Corporation
- James W. Dawson
- G11 - INFORMATION STORAGE
Information Patent Application
Method for skip over redundancy decode with very low overhead
- Publication number 20050226063
- Publication date Oct 13, 2005
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated system logic and abist data compression for an SRAM dire...
- Publication number 20040205434
- Publication date Oct 14, 2004
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Application
Non-binary address generation for ABIST
- Publication number 20040205435
- Publication date Oct 14, 2004
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Application
ABIST address generation
- Publication number 20040205405
- Publication date Oct 14, 2004
- International Business Machines Corporation
- Thomas J. Knips
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for ABIST diagnostics
- Publication number 20020157051
- Publication date Oct 24, 2002
- International Business Machines Corporation
- Joseph E. Eckelman
- G06 - COMPUTING CALCULATING COUNTING

Thomas J. Knips

Person

Patents Grantslast 30 patents

Testing bit write operation to a memory array in integrated circuits

Failing address registers for built-in self tests

Testing multi-port array in integrated circuits

Partition-able storage of test results using inactive storage elements

Built-in testing of unused element on chip

Built-in testing of unused element on chip

AC ABIST diagnostic method, apparatus and program product

Efficient memory product for test and soft repair of SRAM with redu...

Method for self-correcting cache using line delete, data logging, a...

Efficient method of test and soft repair of SRAM with redundancy

ABIST data compression and serialization for memory built-in self t...

Method and apparatus for providing flexible modular redundancy allo...

Integrated system logic and ABIST data compression for an SRAM dire...

Fast pulse powered NOR decode apparatus with pulse stretching and r...

Method and apparatus for ABIST diagnostics

Non-binary address generation for ABIST

ABIST address generation

Apparatus and method for implementing multiple memory redundancy wi...

Method and apparatus for implementing multiple column redundancy fo...

Method for skip over redundancy decode with very low overhead

System for implementing a column redundancy scheme for arrays with...

Patents Applicationslast 30 patents

TESTING BIT WRITE OPERATION TO A MEMORY ARRAY IN INTEGRATED CIRCUITS

FAILING ADDRESS REGISTERS FOR BUILT-IN SELF TESTS

PARTITION-ABLE STORAGE OF TEST RESULTS USING INACTIVE STORAGE ELEMENTS

BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP

BUILT-IN TESTING OF UNUSED ELEMENT ON CHIP

AC ABIST Diagnostic Method, Apparatus and Program Product

Efficient Memory Product for Test and Soft Repair of SRAM with Redu...

Apparatus and method for self-correcting cache using line delete, d...

Efficient method of test and soft repair of SRAM with redundancy

Fast pulse powered NOR decode apparatus with pulse stretching and r...

Method and apparatus for providing flexible modular redundancy allo...

ABIST data compression and serialization for memory built-in self t...

Method for skip over redundancy decode with very low overhead

Integrated system logic and abist data compression for an SRAM dire...

Non-binary address generation for ABIST

ABIST address generation

Method and apparatus for ABIST diagnostics