Thomas J. Snethen

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Endwell, NY, US

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Patents Grantslast 30 patents

Information Patent Grant
Test pattern generation in residue networks
- Patent number 7,587,646
- Issue date Sep 8, 2009
- Cadence Design Systems, Inc.
- Thomas James Snethen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic random LBIST
- Patent number 6,708,305
- Issue date Mar 16, 2004
- International Business Machines Corporation
- L. Owen Farnsworth
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid partial scan method
- Patent number 5,691,990
- Issue date Nov 25, 1997
- International Business Machines Corporation
- Rohit Kapur
- G01 - MEASURING TESTING
Information Patent Grant
Logic network test system with simulator oriented fault test generator
- Patent number 3,961,250
- Issue date Jun 1, 1976
- International Business Machines Corporation
- Thomas J. Snethen
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Efficiency of fault simulation by logic backtracking
- Publication number 20020188904
- Publication date Dec 12, 2002
- International Business Machines Corporation
- Xinghao Chen
- G01 - MEASURING TESTING